From: Mugunthan V N <mugunthanvnm@ti.com>
To: Florian Fainelli <f.fainelli@gmail.com>
Cc: netdev <netdev@vger.kernel.org>, Ben Hutchings <ben@decadent.org.uk>
Subject: Re: TI CPSW Ethernet Tx performance regression
Date: Tue, 4 Feb 2014 14:16:22 +0530 [thread overview]
Message-ID: <52F0A8DE.8080302@ti.com> (raw)
In-Reply-To: <CAGVrzcY5jm+1+B1eqn4Li8K6ovDHCfKwuddqXHgLy_gFNs1KuA@mail.gmail.com>
Hi
On Tuesday 04 February 2014 12:54 AM, Florian Fainelli wrote:
> Ok,the priv pointer when we enter the interrupt handler could point to
> e.g: slave 0, so we need to get it re-assigned to the second slave
> using cpsw_get_slave_priv(). How do you ensure that "priv" at the
> beginning of the interrupt handler does not already point to slave 1?
> In that case, is not there a chance to starve slave 0, or at least
> cause an excessive latency by exiting the interrupt handler for slave
> 1, and then re-entering it for slave 0?
devm_request_irq is called with slave 0 priv, so at the beginning of the
interrupt it is always slave 0 priv irrespective whether the slave 0
interface is up or not.
Regards
Mugunthan V N
prev parent reply other threads:[~2014-02-04 8:46 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-15 12:48 TI CPSW Ethernet Tx performance regression Mugunthan V N
2014-01-15 17:54 ` Ben Hutchings
2014-01-15 21:21 ` Florian Fainelli
2014-01-16 6:07 ` Mugunthan V N
2014-01-16 23:35 ` Florian Fainelli
2014-02-03 18:34 ` Mugunthan V N
2014-02-03 19:24 ` Florian Fainelli
2014-02-04 8:46 ` Mugunthan V N [this message]
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