From mboxrd@z Thu Jan  1 00:00:00 1970
From: Roger Quadros <rogerq@ti.com>
Subject: Re: [PATCH v2 1/3] can: c_can_platform: Fix c_can_hw_raminit_ti()
 and add timeout
Date: Tue, 9 Sep 2014 17:54:26 +0300
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To: Nishanth Menon <nm@ti.com>, <wg@grandegger.com>,
	<mkl@pengutronix.de>
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On 09/09/2014 05:51 PM, Nishanth Menon wrote:
> On 09/09/2014 09:45 AM, Roger Quadros wrote:
> [...]
>>>>  	/* We look only at the bits of our instance. */
>>>>  	val &= mask;
>>>> -	while ((readl(priv->raminit_ctrlreg) & mask) != val)
>>>> +	while ((readl(priv->raminit_ctrlreg) & mask) != val) {
>>>>  		udelay(1);
>>>> +		timeout++;
>>>> +
>>>> +		if (timeout == 1000) {
>>>
>>> How did we come up with this number?
>>
>> wild guess ;), that it should be set in a few microseconds and the delay is not too
>> large.
>>
>> Till I don't hear from hardware guys, it will remain a guess.
>>
> 
> in cases like these, I suggest using emperical data as point ->
> example doing some 10,000 iterations of the operation and picking up
> the worse case number and double it.

In my tests the bit was either set immediately or never at all.
Not sure if we should increase it further.

> 
> Either way, you need to document the same, else a few years down the
> line, when that number is in question, no one will know what it's
> basis was..
> 

OK. I'll add a comment there.

cheers,
-roger