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From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
To: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>,
	Antoine Tenart <antoine.tenart@free-electrons.com>
Cc: thomas.petazzoni@free-electrons.com, zmxu@marvell.com,
	devicetree@vger.kernel.org, netdev@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	alexandre.belloni@free-electrons.com, jszhang@marvell.com,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v5 09/10] ARM: dts: berlin: add the Ethernet node
Date: Mon, 29 Sep 2014 16:34:02 +0200	[thread overview]
Message-ID: <54296DDA.8000400@gmail.com> (raw)
In-Reply-To: <5425A178.4050501@cogentembedded.com>

On 09/26/2014 07:25 PM, Sergei Shtylyov wrote:
> On 09/26/2014 06:33 PM, Antoine Tenart wrote:
>> This patch adds the Ethernet node, enabling the network unit on Berlin
>> BG2Q SoCs.
>
>> Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
>> Acked-by: Arnd Bergmann <arnd@arndb.de>
>> ---
>>   arch/arm/boot/dts/berlin2q.dtsi | 17 +++++++++++++++++
>>   1 file changed, 17 insertions(+)
>
>> diff --git a/arch/arm/boot/dts/berlin2q.dtsi
>> b/arch/arm/boot/dts/berlin2q.dtsi
>> index 902eddb19cd8..d442b22fd1ea 100644
>> --- a/arch/arm/boot/dts/berlin2q.dtsi
>> +++ b/arch/arm/boot/dts/berlin2q.dtsi
>> @@ -114,6 +114,23 @@
>>               #interrupt-cells = <3>;
>>           };
>>
>> +        eth0: ethernet@b90000 {
>> +            compatible = "marvell,pxa168-eth";
>> +            reg = <0xb90000 0x10000>;
>> +            clocks = <&chip CLKID_GETH0>;
>> +            interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
>> +            /* set by bootloader */
>> +            local-mac-address = [00 00 00 00 00 00];
>> +            #address-cells = <1>;
>> +            #size-cells = <0>;
>> +            phy-handle = <&ethphy0>;
>> +            status = "disabled";
>> +
>> +            ethphy0: ethernet-phy@0 {
>> +                reg = <0>;
>> +            };
>> +        };
>> +
>
>     Hm, is the PHY internal to the Ethernet controller?

Sergei,

at least for BG2 and BG2CD the PHY is internal to the SoC. Also,
MDIO bus is part of the ethernet IP, so placing the PHY inside
the combined Ethernet/MDIO IP node is sane.

Sebastian

  reply	other threads:[~2014-09-29 14:34 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-09-26 14:33 [PATCH v6 00/10] ARM: Berlin: Ethernet support Antoine Tenart
2014-09-26 14:33 ` [PATCH v5 01/10] net: pxa168_eth: clean up Antoine Tenart
2014-09-26 14:33 ` [PATCH v5 02/10] net: pxa168_eth: add device tree support Antoine Tenart
2014-09-29 20:04   ` David Miller
2014-09-30 14:28     ` Antoine Tenart
2014-09-26 14:33 ` [PATCH v5 03/10] Documentation: bindings: net: add the Marvell PXA168 Ethernet controller Antoine Tenart
2014-09-26 14:33 ` [PATCH v5 04/10] net: pxa168_eth: fix Ethernet flow control status Antoine Tenart
2014-09-26 14:33 ` [PATCH v5 05/10] net: pxa168_eth: set the mac address on the Ethernet controller Antoine Tenart
2014-09-26 14:33 ` [PATCH v5 06/10] net: pxa168_eth: rework the MAC address setup Antoine Tenart
2014-09-26 14:33 ` [PATCH v5 07/10] net: pxa168_eth: allow Berlin SoCs to use the pxa168_eth driver Antoine Tenart
2014-09-26 14:33 ` [PATCH v5 08/10] net: pxa168_eth: allow to compile the pxa168_eth driver for tests Antoine Tenart
2014-09-26 14:33 ` [PATCH v5 09/10] ARM: dts: berlin: add the Ethernet node Antoine Tenart
2014-09-26 17:25   ` Sergei Shtylyov
2014-09-29 14:34     ` Sebastian Hesselbarth [this message]
2014-09-26 14:33 ` [PATCH v5 10/10] ARM: dts: berlin: enable the Ethernet port on the BG2Q DMP Antoine Tenart
2014-09-26 14:37 ` [PATCH v6 00/10] ARM: Berlin: Ethernet support Antoine Tenart

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