* [PATCH 1/1] drivers: net: cpsw: Fix TX_IN_SEL offset
@ 2014-11-14 14:42 John Ogness
2014-11-14 18:23 ` Mugunthan V N
2014-11-16 19:20 ` David Miller
0 siblings, 2 replies; 3+ messages in thread
From: John Ogness @ 2014-11-14 14:42 UTC (permalink / raw)
To: linux-kernel
Cc: davem, mugunthanvnm, balbi, george.cherian, jhovold, mpa,
bhutchings, zonque, tklauser, netdev
The TX_IN_SEL offset for the CPSW_PORT/TX_IN_CTL register was
incorrect. This caused the Dual MAC mode to never get set when
it should. It also caused possible unintentional setting of a
bit in the CPSW_PORT/TX_BLKS_REM register.
The purpose of setting the Dual MAC mode for this register is to:
"... allow packets from both ethernet ports to be written into
the FIFO without one port starving the other port."
- AM335x ARM TRM
Signed-off-by: John Ogness <john.ogness@linutronix.de>
---
drivers/net/ethernet/ti/cpsw.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index d879448..c560f9a 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -129,9 +129,9 @@ do { \
#define CPSW_VLAN_AWARE BIT(1)
#define CPSW_ALE_VLAN_AWARE 1
-#define CPSW_FIFO_NORMAL_MODE (0 << 15)
-#define CPSW_FIFO_DUAL_MAC_MODE (1 << 15)
-#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15)
+#define CPSW_FIFO_NORMAL_MODE (0 << 16)
+#define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
+#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
#define CPSW_INTPACEEN (0x3f << 16)
#define CPSW_INTPRESCALE_MASK (0x7FF << 0)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH 1/1] drivers: net: cpsw: Fix TX_IN_SEL offset
2014-11-14 14:42 [PATCH 1/1] drivers: net: cpsw: Fix TX_IN_SEL offset John Ogness
@ 2014-11-14 18:23 ` Mugunthan V N
2014-11-16 19:20 ` David Miller
1 sibling, 0 replies; 3+ messages in thread
From: Mugunthan V N @ 2014-11-14 18:23 UTC (permalink / raw)
To: John Ogness, linux-kernel
Cc: davem, balbi, george.cherian, jhovold, mpa, bhutchings, zonque,
tklauser, netdev
On Friday 14 November 2014 08:12 PM, John Ogness wrote:
> The TX_IN_SEL offset for the CPSW_PORT/TX_IN_CTL register was
> incorrect. This caused the Dual MAC mode to never get set when
> it should. It also caused possible unintentional setting of a
> bit in the CPSW_PORT/TX_BLKS_REM register.
>
> The purpose of setting the Dual MAC mode for this register is to:
>
> "... allow packets from both ethernet ports to be written into
> the FIFO without one port starving the other port."
> - AM335x ARM TRM
>
> Signed-off-by: John Ogness <john.ogness@linutronix.de>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Regards
Mugunthan V N
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH 1/1] drivers: net: cpsw: Fix TX_IN_SEL offset
2014-11-14 14:42 [PATCH 1/1] drivers: net: cpsw: Fix TX_IN_SEL offset John Ogness
2014-11-14 18:23 ` Mugunthan V N
@ 2014-11-16 19:20 ` David Miller
1 sibling, 0 replies; 3+ messages in thread
From: David Miller @ 2014-11-16 19:20 UTC (permalink / raw)
To: john.ogness
Cc: linux-kernel, mugunthanvnm, balbi, george.cherian, jhovold, mpa,
bhutchings, zonque, tklauser, netdev
From: John Ogness <john.ogness@linutronix.de>
Date: Fri, 14 Nov 2014 15:42:52 +0100
> The TX_IN_SEL offset for the CPSW_PORT/TX_IN_CTL register was
> incorrect. This caused the Dual MAC mode to never get set when
> it should. It also caused possible unintentional setting of a
> bit in the CPSW_PORT/TX_BLKS_REM register.
>
> The purpose of setting the Dual MAC mode for this register is to:
>
> "... allow packets from both ethernet ports to be written into
> the FIFO without one port starving the other port."
> - AM335x ARM TRM
>
> Signed-off-by: John Ogness <john.ogness@linutronix.de>
Applied, thanks.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2014-11-14 14:42 [PATCH 1/1] drivers: net: cpsw: Fix TX_IN_SEL offset John Ogness
2014-11-14 18:23 ` Mugunthan V N
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