From mboxrd@z Thu Jan  1 00:00:00 1970
From: Amir Vadai <amirv@mellanox.com>
Subject: Re: [PATCH net] net/mlx4: Cache line CQE/EQE stride fixes
Date: Tue, 16 Dec 2014 14:29:11 +0200
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Cc: "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
	Yevgeny Petrilin <yevgenyp@mellanox.com>,
	Or Gerlitz <ogerlitz@mellanox.com>,
	"clsoto@linux.vnet.ibm.com" <clsoto@linux.vnet.ibm.com>,
	Ido Shamay <idos@mellanox.com>,
	Wei Yang <weiyang@linux.vnet.ibm.com>
To: "David S. Miller" <davem@davemloft.net>
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On 12/16/2014 1:28 PM, Amir Vadai wrote:
> From: Ido Shamay <idos@mellanox.com>
> 
> This commit contains 2 fixes for the 128B CQE/EQE stride feaure.
> Wei found that mlx4_QUERY_HCA function marked the wrong capability
> in flags (64B CQE/EQE), when CQE/EQE stride feature was enabled.
> Also added small fix in initial CQE ownership bit assignment, when CQE
> is size is not default 32B.
> 
> Fixes: 77507aa24 (net/mlx4: Enable CQE/EQE stride support)
> Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
> Signed-off-by: Ido Shamay <idos@mellanox.com>
> Signed-off-by: Amir Vadai <amirv@mellanox.com>
> ---
> Dave Hi,
> 
> Please pull this patch also to stable (at least 3.17)
> 
> Thanks,
> Amir

Small correction: Should pull into -stable >= 3.18

Amir