From mboxrd@z Thu Jan 1 00:00:00 1970 From: Nicolas Schichan Subject: Re: [PATCH] bcm63xx_enet: fix poll callback. Date: Tue, 03 Mar 2015 15:43:28 +0100 Message-ID: <54F5C890.7080403@freebox.fr> References: <1425383112-23851-1-git-send-email-nschichan@freebox.fr> <1425389399.5130.169.camel@edumazet-glaptop2.roam.corp.google.com> <1425390142.5130.173.camel@edumazet-glaptop2.roam.corp.google.com> <54F5BCE0.3060507@freebox.fr> <1425392282.5130.176.camel@edumazet-glaptop2.roam.corp.google.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Cc: "David S. Miller" , Tobias Klauser , Felipe Balbi , Wilfried Klaebe , "Eric W. Biederman" , Alexander Duyck , netdev@vger.kernel.org, linux-kernel@vger.kernel.org To: Eric Dumazet Return-path: In-Reply-To: <1425392282.5130.176.camel@edumazet-glaptop2.roam.corp.google.com> Sender: linux-kernel-owner@vger.kernel.org List-Id: netdev.vger.kernel.org On 03/03/2015 03:18 PM, Eric Dumazet wrote: > On Tue, 2015-03-03 at 14:53 +0100, Nicolas Schichan wrote: >> On 03/03/2015 02:42 PM, Eric Dumazet wrote: >>>> To avoid that, I would take priv->tx_lock only once, or add a limit on >>>> the number of skbs that can be drained per round. >>> >>> Something like this (untested) patch >> >> I'm not against testing this patch, but we do not have any SMP capable bcm63xx >> board here so I don't think it will be of any use. >> >> bcm6358 and bcm6368 do indeed have two MIPS threads, but SMP is not possible >> (due to a data cache or TLB shared across all MIPS threads , unbearably >> complicating things, IIRC). >> >> bcm63xx ARM SoCs look like they can support SMP though. >> >> Regards, >> > > I am reasonably confident the patch is OK, but I cannot easily compile > it on my laptop (x86_64) : Okay, I gave your patch a go and it works correctly on our non-SMP capable boards (and with DEBUG_SPINLOCK=y). Feel free to add: Tested-by: Nicolas Schichan Regards, -- Nicolas Schichan Freebox SAS