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From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
To: Jaeden Amero <jaeden.amero@ni.com>,
	Florian Fainelli <f.fainelli@gmail.com>,
	netdev@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 3/3] net/phy: micrel: Center FLP timing at 16ms
Date: Sat, 06 Jun 2015 00:09:59 +0300	[thread overview]
Message-ID: <55721027.6030509@cogentembedded.com> (raw)
In-Reply-To: <1433534130-16323-4-git-send-email-jaeden.amero@ni.com>

Hello.

On 06/05/2015 10:55 PM, Jaeden Amero wrote:

> Link failures have been observed when using the KSZ9031 with HP 1810-8G
> and HP 1910-8G network switches. Center the FLP timing at 16ms to help
> avoid intermittent link failures.

>  From the KSZ9031RNX and KSZ9031MNX data sheets revision 2.2, section
> "Auto-Negotiation Timing":
> 	The KSZ9031[RNX or MNX] Fast Link Pulse (FLP) burst-to-burst
> 	transmit timing for Auto-Negotiation defaults to 8ms. IEEE 802.3
> 	Standard specifies this timing to be 16ms +/-8ms. Some PHY link
> 	partners need to receive the FLP with 16ms centered timing;
> 	otherwise, there can be intermittent link failures and long
> 	link-up times.

> 	After KSZ9031[RNX or MNX] power-up/reset, program the following
> 	register sequence to set the FLP timing to 16ms

> 	Write Register Dh = 0x0000 // Set up register address for MMD – Device Address 0h
> 	Write Register Eh = 0x0004 // Select Register 4h of MMD – Device Address 0h
> 	Write Register Dh = 0x4000 // Select register data for MMD – Device Address 0h, Register 4h
> 	Write Register Eh = 0x0006 // Write value 0x0006 to MMD – Device Address 0h, Register 4h
> 	Write Register Dh = 0x0000 // Set up register address for MMD – Device Address 0h
> 	Write Register Eh = 0x0003 // Select Register 3h of MMD – Device Address 0h
> 	Write Register Dh = 0x4000 // Select register data for MMD – Device Address 0h, Register 3h
> 	Write Register Eh = 0x1A80 // Write value 0x1A80 to MMD – Device Address 0h, Register 3h
> 	Write Register 0h, Bit [9] = 1 // Restart Auto-Negotiation

> Signed-off-by: Jaeden Amero <jaeden.amero@ni.com>
> ---
>   drivers/net/phy/micrel.c | 26 +++++++++++++++++++++++++-
>   1 file changed, 25 insertions(+), 1 deletion(-)

> diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
> index f23765e..e156e36 100644
> --- a/drivers/net/phy/micrel.c
> +++ b/drivers/net/phy/micrel.c
[...]
> @@ -441,6 +461,7 @@ static int ksz9031_config_init(struct phy_device *phydev)
>   		"txd2-skew-ps", "txd3-skew-ps"
>   	};
>   	static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
> +	int result;

    You hardly need this variable...

>
>   	if (!of_node && dev->parent->of_node)
>   		of_node = dev->parent->of_node;
> @@ -462,7 +483,10 @@ static int ksz9031_config_init(struct phy_device *phydev)
>   				MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
>   				tx_data_skews, 4);
>   	}
> -	return 0;
> +
> +	result = ksz9031_center_flp_timing(phydev);
> +
> +	return result;

    Why not just return directly?

[...]

WBR, Sergei

  reply	other threads:[~2015-06-05 21:09 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-05 19:55 [PATCH v2 0/3] net/phy: micrel: Center FLP timing at 16ms Jaeden Amero
2015-06-05 19:55 ` [PATCH v2 1/3] net/phy: micrel: Be more const correct Jaeden Amero
2015-06-05 19:55 ` [PATCH v2 2/3] net/phy: micrel: Comment MMD address of extended registers Jaeden Amero
2015-06-05 19:55 ` [PATCH v2 3/3] net/phy: micrel: Center FLP timing at 16ms Jaeden Amero
2015-06-05 21:09   ` Sergei Shtylyov [this message]
2015-06-05 22:36     ` Jaeden Amero

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