[PATCH net] amd-xgbe: Fix race between access of desc and desc index

[PATCH net] amd-xgbe: Fix race between access of desc and desc index

[Tom Lendacky]

During Tx cleanup it's still possible for the descriptor data to be
read ahead of the descriptor index. A memory barrier is required between
the read of the descriptor index and the start of the Tx cleanup loop.
This allows a change to a lighter-weight barrier in the Tx transmit
routine just before updating the current descriptor index.

Since the memory barrier does result in extra overhead on arm64, keep
the previous change to not chase the current descriptor value. This
prevents the execution of the barrier for each loop performed.

Suggested-by: Alexander Duyck <alexander.duyck@gmail.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
---
 drivers/net/ethernet/amd/xgbe/xgbe-dev.c |    2 +-
 drivers/net/ethernet/amd/xgbe/xgbe-drv.c |    4 ++++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
index e9ab8b9..f672dba 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
@@ -1595,7 +1595,7 @@ static void xgbe_dev_xmit(struct xgbe_channel *channel)
 				  packet->rdesc_count, 1);
 
 	/* Make sure ownership is written to the descriptor */
-	wmb();
+	smp_wmb();
 
 	ring->cur = cur_index + 1;
 	if (!packet->skb->xmit_more ||
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c
index d2b77d9..dde0486 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c
@@ -1816,6 +1816,10 @@ static int xgbe_tx_poll(struct xgbe_channel *channel)
 		return 0;
 
 	cur = ring->cur;
+
+	/* Be sure we get ring->cur before accessing descriptor data */
+	smp_rmb();
+
 	txq = netdev_get_tx_queue(netdev, channel->queue_index);
 
 	while ((processed < XGBE_TX_DESC_MAX_PROC) &&

Re: [PATCH net] amd-xgbe: Fix race between access of desc and desc index

[David Miller]

From: Tom Lendacky <thomas.lendacky@amd.com>
Date: Mon, 26 Oct 2015 17:13:54 -0500

> During Tx cleanup it's still possible for the descriptor data to be
> read ahead of the descriptor index. A memory barrier is required between
> the read of the descriptor index and the start of the Tx cleanup loop.
> This allows a change to a lighter-weight barrier in the Tx transmit
> routine just before updating the current descriptor index.
> 
> Since the memory barrier does result in extra overhead on arm64, keep
> the previous change to not chase the current descriptor value. This
> prevents the execution of the barrier for each loop performed.
> 
> Suggested-by: Alexander Duyck <alexander.duyck@gmail.com>
> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>

Applied, thanks.

Re: [PATCH net] amd-xgbe: Fix race between access of desc and desc index

[Tom Lendacky]

On 10/27/2015 09:50 PM, David Miller wrote:
> From: Tom Lendacky <thomas.lendacky@amd.com>
> Date: Mon, 26 Oct 2015 17:13:54 -0500
>
>> During Tx cleanup it's still possible for the descriptor data to be
>> read ahead of the descriptor index. A memory barrier is required between
>> the read of the descriptor index and the start of the Tx cleanup loop.
>> This allows a change to a lighter-weight barrier in the Tx transmit
>> routine just before updating the current descriptor index.
>>
>> Since the memory barrier does result in extra overhead on arm64, keep
>> the previous change to not chase the current descriptor value. This
>> prevents the execution of the barrier for each loop performed.
>>
>> Suggested-by: Alexander Duyck <alexander.duyck@gmail.com>
>> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
>
> Applied, thanks.
>

Thanks David.  Could you queue this up for the 4.1 and 4.2 stable
trees?

Thanks,
Tom

Re: [PATCH net] amd-xgbe: Fix race between access of desc and desc index

[David Miller]

From: Tom Lendacky <thomas.lendacky@amd.com>
Date: Wed, 28 Oct 2015 08:48:36 -0500

> On 10/27/2015 09:50 PM, David Miller wrote:
>> From: Tom Lendacky <thomas.lendacky@amd.com>
>> Date: Mon, 26 Oct 2015 17:13:54 -0500
>>
>>> During Tx cleanup it's still possible for the descriptor data to be
>>> read ahead of the descriptor index. A memory barrier is required
>>> between
>>> the read of the descriptor index and the start of the Tx cleanup loop.
>>> This allows a change to a lighter-weight barrier in the Tx transmit
>>> routine just before updating the current descriptor index.
>>>
>>> Since the memory barrier does result in extra overhead on arm64, keep
>>> the previous change to not chase the current descriptor value. This
>>> prevents the execution of the barrier for each loop performed.
>>>
>>> Suggested-by: Alexander Duyck <alexander.duyck@gmail.com>
>>> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
>>
>> Applied, thanks.
>>
> 
> Thanks David.  Could you queue this up for the 4.1 and 4.2 stable
> trees?

Ok, done.