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From: Florian Fainelli <f.fainelli@gmail.com>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	netdev@vger.kernel.org
Cc: slash.tmp@free.fr
Subject: Re: [PATCH 4/4] net: phy: at803x: Add the interrupt register bit definitions
Date: Sat, 26 Dec 2015 19:29:22 -0800	[thread overview]
Message-ID: <567F5B12.4080301@gmail.com> (raw)
In-Reply-To: <1451089622-14957-5-git-send-email-martin.blumenstingl@googlemail.com>

Le 25/12/2015 16:27, Martin Blumenstingl a écrit :
> Also use them instead of a magic value when enabling the interrupts.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>

> ---
>  drivers/net/phy/at803x.c | 32 +++++++++++++++++++++++---------
>  1 file changed, 23 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
> index 6e8aafd..edb0a5f 100644
> --- a/drivers/net/phy/at803x.c
> +++ b/drivers/net/phy/at803x.c
> @@ -20,13 +20,21 @@
>  #include <linux/gpio/consumer.h>
>  
>  #define AT803X_INTR_ENABLE			0x12
> -#define AT803X_INTR_ENABLE_INIT			0xec00
> +#define AT803X_INTR_ENABLE_AUTONEG_ERR		BIT(15)
> +#define AT803X_INTR_ENABLE_SPEED_CHANGED	BIT(14)
> +#define AT803X_INTR_ENABLE_DUPLEX_CHANGED	BIT(13)
> +#define AT803X_INTR_ENABLE_PAGE_RECEIVED	BIT(12)
> +#define AT803X_INTR_ENABLE_LINK_FAIL		BIT(11)
> +#define AT803X_INTR_ENABLE_LINK_SUCCESS		BIT(10)
> +#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE	BIT(5)
> +#define AT803X_INTR_ENABLE_POLARITY_CHANGED	BIT(1)
> +#define AT803X_INTR_ENABLE_WOL			BIT(0)
> +
>  #define AT803X_INTR_STATUS			0x13
>  
>  #define AT803X_SMART_SPEED			0x14
>  #define AT803X_LED_CONTROL			0x18
>  
> -#define AT803X_WOL_ENABLE			0x01
>  #define AT803X_DEVICE_ADDR			0x03
>  #define AT803X_LOC_MAC_ADDR_0_15_OFFSET		0x804C
>  #define AT803X_LOC_MAC_ADDR_16_31_OFFSET	0x804B
> @@ -179,14 +187,14 @@ static int at803x_set_wol(struct phy_device *phydev,
>  		}
>  
>  		value = phy_read(phydev, AT803X_INTR_ENABLE);
> -		value |= AT803X_WOL_ENABLE;
> +		value |= AT803X_INTR_ENABLE_WOL;
>  		ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
>  		if (ret)
>  			return ret;
>  		value = phy_read(phydev, AT803X_INTR_STATUS);
>  	} else {
>  		value = phy_read(phydev, AT803X_INTR_ENABLE);
> -		value &= (~AT803X_WOL_ENABLE);
> +		value &= (~AT803X_INTR_ENABLE_WOL);
>  		ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
>  		if (ret)
>  			return ret;
> @@ -205,7 +213,7 @@ static void at803x_get_wol(struct phy_device *phydev,
>  	wol->wolopts = 0;
>  
>  	value = phy_read(phydev, AT803X_INTR_ENABLE);
> -	if (value & AT803X_WOL_ENABLE)
> +	if (value & AT803X_INTR_ENABLE_WOL)
>  		wol->wolopts |= WAKE_MAGIC;
>  }
>  
> @@ -217,7 +225,7 @@ static int at803x_suspend(struct phy_device *phydev)
>  	mutex_lock(&phydev->lock);
>  
>  	value = phy_read(phydev, AT803X_INTR_ENABLE);
> -	wol_enabled = value & AT803X_WOL_ENABLE;
> +	wol_enabled = value & AT803X_INTR_ENABLE_WOL;
>  
>  	value = phy_read(phydev, MII_BMCR);
>  
> @@ -310,9 +318,15 @@ static int at803x_config_intr(struct phy_device *phydev)
>  
>  	value = phy_read(phydev, AT803X_INTR_ENABLE);
>  
> -	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
> -		err = phy_write(phydev, AT803X_INTR_ENABLE,
> -				value | AT803X_INTR_ENABLE_INIT);
> +	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
> +		value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
> +		value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
> +		value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
> +		value |= AT803X_INTR_ENABLE_LINK_FAIL;
> +		value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
> +
> +		err = phy_write(phydev, AT803X_INTR_ENABLE, value);
> +	}
>  	else
>  		err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
>  
> 


-- 
Florian

  reply	other threads:[~2015-12-27  3:29 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-12-26  0:26 Small improvements for the at803x PHY driver Martin Blumenstingl
2015-12-26  0:26 ` [PATCH 1/4] net: phy: at803x: Don't set gbit features for the AR8030 phy Martin Blumenstingl
2015-12-27  3:24   ` Florian Fainelli
2015-12-26  0:27 ` [PATCH 2/4] net: phy: at803x: Allow specifying the RGMII RX clock delay via phy mode Martin Blumenstingl
2015-12-27  3:28   ` Florian Fainelli
2015-12-27 15:15     ` Martin Blumenstingl
2015-12-27 20:22     ` Mason
2016-01-04 21:17       ` Martin Blumenstingl
2016-01-04 22:05         ` Florian Fainelli
2015-12-26  0:27 ` [PATCH 3/4] net: phy: at803x: Clean up duplicate register definitions Martin Blumenstingl
2015-12-27  3:28   ` Florian Fainelli
2015-12-26  0:27 ` [PATCH 4/4] net: phy: at803x: Add the interrupt register bit definitions Martin Blumenstingl
2015-12-27  3:29   ` Florian Fainelli [this message]
2015-12-26 11:57 ` Small improvements for the at803x PHY driver Mason
2015-12-27  3:29   ` Florian Fainelli
2016-01-15  0:57     ` Martin Blumenstingl

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