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From: Florian Fainelli <f.fainelli@gmail.com>
To: Dustin Byford <dustin@cumulusnetworks.com>
Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>,
	Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
	netdev@vger.kernel.org
Subject: Re: [PATCH RFC 00/26] Phylink & SFP support
Date: Thu, 07 Jan 2016 12:42:56 -0800	[thread overview]
Message-ID: <568ECDD0.7080307@gmail.com> (raw)
In-Reply-To: <20151228233955.GB3796@cumulusnetworks.com>

On 28/12/15 15:39, Dustin Byford wrote:
>> Using a phandle here allows for quite a lot of flexibility on how you want to associate a given SFP to its data plane partner. I do not think we need to get more strict than that strictly mandate an actual Ethernet controller node. These Marvell adapters typically have one or more " ports", each of them being backed by a netdev. The same could be true with a switch properly modeled.
> 
> On a switch though, the number of "ports" is often configurable.
> Physically the q/sfp cage to ASIC wiring is fixed, but when you've
> plugged in a breakout cable you get four "ports" for a single QSFP cage.
> They act like four separate devices in most ways, the notable exception
> is that they share a QSFP module eeprom and the discrete IOs to the cage
> like "reset" and "interrupt"  At the MAC layer, each port gets an
> independent set of resources and they act like separate netdevs.
> 
> A concrete proposal might be to add a "channel" or "lane" parameter to
> sfp,ethernet with a default of 0.
> 
> sfp,ethernet = <&eth2>
> 
> is equivalent to:
> sfp,ethernet = <&eth2 0>
> 
> 
> SFP on a switch0 device with 128 channels:
> 
> sfp,ethernet = <&switch0 42>
> consumes channel 42
> 
> qsfp,ethernet = <&switch0>
> consumes channels 0-3
> 
> qsfp,ethernet = <&switch0 124 125 126 127>
> consumes channels 124-127
> 
> alternatives:
> 
> (less explicit, assume adjacent channels)
> qsfp,ethernet = <&switch0 124> // consumes 124-127

Right, that does not sound specific enough, because the name is qsfp,
that means quad, and then you do 124 + 4 - 1 to know the last number,
what could possibly go wrong ;)?

> 
> (more explicit, don't assume the same device)
> qsfp,ethernet = <&switch0 124 &switch0 125 &switch0 126 &switch0 127>
> or:
> qsfp,ethernet0 = <&switch0 124>
> qsfp,ethernet1 = <&switch0 125>
> qsfp,ethernet2 = <&switch0 126>
> qsfp,ethernet3 = <&switch0 127>

That might be the best representation actually.

> 
> (move complexity to the NIC/ASIC, ensure one channel per handle on the
> NIC/ASIC side)
> qsfp,ethernet = <&switch0c124 &switch0c125 &switch0c126 &switch0c127>

So counting the number of cells tells you how the QSFP got broken out
into individual SFPs? That could work too, humm.

[snip]

>> Would this be something you expect to happen dynamically? Not that this does not seem reasonable but would these netdevs serve a different purpose than being control endpoints, or would they become real logical netdevs with separate data planes at the MAC they would be linked to?
> 
> Real netdevs with separate data planes.  Reconfiguring them dynamically
> seems like a good theoretical goal but is probably impractical in most
> cases.  Even if it's not dynamic I think it's a good example of why you
> might want a QSFP device to have an ethernet handle that points to four
> things instead of one.

Agreed.
-- 
Florian

  reply	other threads:[~2016-01-07 20:43 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-12-07 17:35 [PATCH RFC 00/26] Phylink & SFP support Russell King - ARM Linux
2015-12-07 17:37 ` [PATCH RFC 01/26] phy: move fixed_phy MII register generation to a library Russell King
2016-01-07 19:47   ` Florian Fainelli
2015-12-07 17:37 ` [PATCH RFC 02/26] phy: convert swphy register generation to tabular form Russell King
2016-01-07 19:47   ` Florian Fainelli
2015-12-07 17:37 ` [PATCH RFC 03/26] phy: separate swphy state validation from register generation Russell King
2016-01-07 19:48   ` Florian Fainelli
2015-12-07 17:37 ` [PATCH RFC 04/26] phy: generate swphy registers on the fly Russell King
2016-01-07 19:49   ` Florian Fainelli
2015-12-07 17:37 ` [PATCH RFC 05/26] phy: improve safety of fixed-phy MII register reading Russell King
2016-01-07 19:50   ` Florian Fainelli
2015-12-07 17:37 ` [PATCH RFC 06/26] phy: provide a hook for link up/link down events Russell King
2016-01-07 19:53   ` Florian Fainelli
2015-12-07 17:37 ` [PATCH RFC 07/26] phy: marvell: 88E1512: add flow control support Russell King
2016-01-07 19:53   ` Florian Fainelli
2015-12-07 17:37 ` [PATCH RFC 08/26] phy: export phy_start_machine() for phylink Russell King
2016-01-07 19:53   ` Florian Fainelli
2015-12-07 17:37 ` [PATCH RFC 09/26] phy: export phy_speed_to_str() " Russell King
2016-01-07 19:54   ` Florian Fainelli
2015-12-07 17:38 ` [PATCH RFC 10/26] phy: add I2C mdio bus Russell King
2015-12-08 18:15   ` Florian Fainelli
2015-12-11 10:25     ` Russell King - ARM Linux
2015-12-07 17:38 ` [PATCH RFC 11/26] phylink: add phylink infrastructure Russell King
2016-01-07 20:09   ` Florian Fainelli
2015-12-07 17:38 ` [PATCH RFC 12/26] phylink: add hooks for SFP support Russell King
2016-01-07 20:05   ` Florian Fainelli
2015-12-07 17:38 ` [PATCH RFC 13/26] sfp: add phylink based SFP module support Russell King
2016-01-07 20:23   ` Florian Fainelli
2015-12-07 17:38 ` [PATCH RFC 14/26] sfp: display SFP module information Russell King
2016-01-07 20:23   ` Florian Fainelli
2015-12-07 17:38 ` [PATCH RFC 15/26] net: mvneta: convert to phylink Russell King
2016-01-07 20:22   ` Florian Fainelli
2015-12-07 17:38 ` [PATCH RFC 16/26] phy: fixed-phy: remove fixed_phy_update_state() Russell King
2016-01-07 20:15   ` Florian Fainelli
2015-12-07 17:38 ` [PATCH RFC 17/26] phylink: add ethtool nway_reset support Russell King
2016-01-07 20:24   ` Florian Fainelli
2015-12-07 17:38 ` [PATCH RFC 18/26] net: mvneta: add " Russell King
2016-01-07 20:19   ` Florian Fainelli
2015-12-07 17:38 ` [PATCH RFC 19/26] phylink: add flow control support Russell King
2016-01-07 20:25   ` Florian Fainelli
2015-12-07 17:38 ` [PATCH RFC 20/26] net: mvneta: add flow control support via phylink Russell King
2016-01-07 20:26   ` Florian Fainelli
2015-12-07 17:38 ` [PATCH RFC 21/26] net: mvneta: enable flow control for PHY connections Russell King
2016-01-07 20:31   ` Florian Fainelli
2015-12-07 17:39 ` [PATCH RFC 22/26] phylink: add EEE support Russell King
2016-01-07 20:34   ` Florian Fainelli
2015-12-07 17:39 ` [PATCH RFC 23/26] net: mvneta: " Russell King
2016-01-07 20:35   ` Florian Fainelli
2015-12-07 17:39 ` [PATCH RFC 24/26] phylink: add module EEPROM support Russell King
2016-01-07 20:36   ` Florian Fainelli
2015-12-07 17:39 ` [PATCH RFC 25/26] net: mvneta: add module EEPROM reading support Russell King
2016-01-07 20:36   ` Florian Fainelli
2015-12-07 17:39 ` [PATCH RFC 26/26] sfp/phylink: hook up eeprom functions Russell King
2015-12-15  7:26 ` [PATCH RFC 00/26] Phylink & SFP support Dustin Byford
2015-12-28  2:08   ` Florian Fainelli
2015-12-28 23:39     ` Dustin Byford
2016-01-07 20:42       ` Florian Fainelli [this message]
2015-12-28  1:56 ` Florian Fainelli

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