From mboxrd@z Thu Jan  1 00:00:00 1970
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Subject: Re: [patch net 2/2] mlxsw: pci: Correctly determine if descriptor
 queue is full
Date: Mon, 7 Mar 2016 17:04:59 +0300
Message-ID: <56DD8A8B.8000705@cogentembedded.com>
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To: Jiri Pirko <jiri@resnulli.us>, netdev@vger.kernel.org
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Hello.

On 3/7/2016 11:24 AM, Jiri Pirko wrote:

> From: Ido Schimmel <idosch@mellanox.com>
>
> The descriptor queues for sending (SDQs) and receiving (RDQs) packets
> are managed by two counters - producer and consumer - which are both
> 16-bit in size. A queue is considered full when the difference between
> the two equals the queue's maximum number of descriptors.
>
> However, if the producer counter overflows, then it's possible for the
> full queue check to fail, as it doesn't take the overflow into account.
> In such a case, descriptors already passed to the device - but for which
> a completion has yet to be posted - will be overwritten, thereby causing
> undefined behavior. The above can be achieved under heavy load (~30
> netperf instances).
>
> Fix that by casting the substraction result to u16, preventing it from

    Subtraction.

> being treated as a signed integer.
>
> Fixes: eda6500a987a ("mlxsw: Add PCI bus implementation")
> Signed-off-by: Ido Schimmel <idosch@mellanox.com>
> Signed-off-by: Jiri Pirko <jiri@mellanox.com>

[...]

MBR, Sergei