From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sergei Shtylyov Subject: Re: [PATCH v3 net-next] ravb: do not write 1 to reserved bits Date: Tue, 18 Sep 2018 19:56:45 +0300 Message-ID: <56bacfca-e2a9-fbad-77cc-5c06d10f0648@cogentembedded.com> References: <20180918102226.8017-1-horms+renesas@verge.net.au> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Cc: Magnus Damm , netdev@vger.kernel.org, linux-renesas-soc@vger.kernel.org To: Simon Horman , David Miller Return-path: Received: from mail-lj1-f193.google.com ([209.85.208.193]:34324 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730072AbeIRWaP (ORCPT ); Tue, 18 Sep 2018 18:30:15 -0400 Received: by mail-lj1-f193.google.com with SMTP id f8-v6so2439821ljk.1 for ; Tue, 18 Sep 2018 09:56:48 -0700 (PDT) In-Reply-To: <20180918102226.8017-1-horms+renesas@verge.net.au> Content-Language: en-MW Sender: netdev-owner@vger.kernel.org List-ID: On 09/18/2018 01:22 PM, Simon Horman wrote: > From: Kazuya Mizuguchi > > EtherAVB hardware requires 0 to be written to status register bits in > order to clear them, however, care must be taken not to: > > 1. Clear other bits, by writing zero to them > 2. Write one to reserved bits > > This patch corrects the ravb driver with respect to the second point above. > This is done by defining reserved bit masks for the affected registers and, > after auditing the code, ensure all sites that may write a one to a > reserved bit use are suitably masked. > > Signed-off-by: Kazuya Mizuguchi > Signed-off-by: Simon Horman BTW, perhaps this should be merged into net.git instead? DaveM, your call? :-) MBR, Sergei