From mboxrd@z Thu Jan  1 00:00:00 1970
From: Florian Fainelli <f.fainelli@gmail.com>
Subject: Re: [PATCH] net: phy: dp83867: Fix initialization of PHYCR register
Date: Sat, 2 Jul 2016 10:01:34 -0700
Message-ID: <5777F36E.6090105@gmail.com>
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To: Stefan Hauser <stefan@shauser.net>, netdev@vger.kernel.org,
	Dan Murphy <dmurphy@ti.com>
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Le 01/07/2016 13:35, Stefan Hauser a =C3=A9crit :
> When initializing the PHY control register, the FIFO depth bits are
> written without reading the previous register value, i.e. all other
> bits are overwritten with zero. This disables automatic MDI-X
> configuration, which is enabled by default. Fix initialization by doi=
ng
> a read/modify/write operation.
>=20
> Signed-off-by: Stefan Hauser <stefan@shauser.net>

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
=46ixes: 2a10154abcb7 ("net: phy: dp83867: Add TI dp83867 phy")
--=20
=46lorian