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[146.241.226.170]) by smtp.gmail.com with ESMTPSA id ff20-20020a05622a4d9400b00403f1a7be90sm237135qtb.88.2023.07.20.04.34.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jul 2023 04:34:28 -0700 (PDT) Message-ID: <5781d16d42ae02742af5ebaaf29875a0779b2d92.camel@redhat.com> Subject: Re: [PATCH net v2] net: phy: marvell10g: fix 88x3310 power up From: Paolo Abeni To: Jiawen Wu , linux@armlinux.org.uk, kabel@kernel.org, andrew@lunn.ch, hkallweit1@gmail.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, netdev@vger.kernel.org Date: Thu, 20 Jul 2023 13:34:25 +0200 In-Reply-To: <20230719092233.137844-1-jiawenwu@trustnetic.com> References: <20230719092233.137844-1-jiawenwu@trustnetic.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.46.4 (3.46.4-1.fc37) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net On Wed, 2023-07-19 at 17:22 +0800, Jiawen Wu wrote: > Clear MV_V2_PORT_CTRL_PWRDOWN bit to set power up for 88x3310 PHY, > it sometimes does not take effect immediately. And a read of this > register causes the bit not to clear. This will cause mv3310_reset() > to time out, which will fail the config initialization. So add a delay > before the next access. >=20 > Fixes: c9cc1c815d36 ("net: phy: marvell10g: place in powersave mode at pr= obe") > Signed-off-by: Jiawen Wu > --- > v1 -> v2: > - change poll-bit-clear to time delay > --- > drivers/net/phy/marvell10g.c | 7 +++++++ > 1 file changed, 7 insertions(+) >=20 > diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c > index 55d9d7acc32e..d4bb90d76881 100644 > --- a/drivers/net/phy/marvell10g.c > +++ b/drivers/net/phy/marvell10g.c > @@ -328,6 +328,13 @@ static int mv3310_power_up(struct phy_device *phydev= ) > ret =3D phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, > MV_V2_PORT_CTRL_PWRDOWN); > =20 > + /* Sometimes, the power down bit doesn't clear immediately, and > + * a read of this register causes the bit not to clear. Delay > + * 100us to allow the PHY to come out of power down mode before > + * the next access. > + */ > + udelay(100); Out of sheer ignorance, would an usleep_range(...) be more appropriate here? Thanks! Paolo