From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86A47C43381 for ; Tue, 19 Feb 2019 15:14:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5913A20665 for ; Tue, 19 Feb 2019 15:14:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727303AbfBSPOX (ORCPT ); Tue, 19 Feb 2019 10:14:23 -0500 Received: from mslow2.mail.gandi.net ([217.70.178.242]:40452 "EHLO mslow2.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726180AbfBSPOX (ORCPT ); Tue, 19 Feb 2019 10:14:23 -0500 Received: from relay9-d.mail.gandi.net (unknown [217.70.183.199]) by mslow2.mail.gandi.net (Postfix) with ESMTP id A588B3A8B37 for ; Tue, 19 Feb 2019 15:06:59 +0000 (UTC) X-Originating-IP: 90.88.23.190 Received: from aptenodytes (aaubervilliers-681-1-81-190.w90-88.abo.wanadoo.fr [90.88.23.190]) (Authenticated sender: paul.kocialkowski@bootlin.com) by relay9-d.mail.gandi.net (Postfix) with ESMTPSA id 9128FFF81E; Tue, 19 Feb 2019 15:06:57 +0000 (UTC) Message-ID: <5a23b65bb9209cab5616ea06cbbb9c86dcaad1df.camel@bootlin.com> Subject: Re: Handling an Extra Signal at PHY Reset From: Paul Kocialkowski To: Andrew Lunn Cc: Florian Fainelli , Heiner Kallweit , netdev@vger.kernel.org, Thomas Petazzoni , =?ISO-8859-1?Q?Myl=E8ne?= Josserand Date: Tue, 19 Feb 2019 16:06:57 +0100 In-Reply-To: <20190219133629.GN14879@lunn.ch> References: <20190219133629.GN14879@lunn.ch> Organization: Bootlin Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.30.5 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Hi Andrew, On Tue, 2019-02-19 at 14:36 +0100, Andrew Lunn wrote: > On Tue, Feb 19, 2019 at 10:14:20AM +0100, Paul Kocialkowski wrote: > > Hi, > > > > We are dealing with an Ethernet PHY (Marvell 88E1512) that comes with a > > CONFIG pin that must be connected to one of the other pins of the PHY > > to configure the LSB of the PHY address as well as I/O voltages (see > > section 2.18.1 Hardware Configuration of the datasheet). It must be > > connected "soon after reset" for the PHY to be correctly configured. > > Hi Paul > > I assume there are two PHYs on the MDIO bus, and you need to ensure > they have different addresses? Do we have an Ethernet switch involved > here, or are they two SoC Ethernet networks with one shared MDIO bus? Thanks for your answer! I think the reason why we need to deal with the CONFIG pin is more about setting the correct I/O voltage than the PHY address (it just happens that the CONFIG pin configures both at once). With our setup, we only have a single PHY and no fancy eth switch setup (although there is a GMII2RGMII converter that is controlled through the MDIO bus, but there is no risk of address conflict). > This seems like an odd design. I've normally seen weak pull up/down > resistors, not a switch, so i'm wondering why it is designed like > this. Yes, that's definitely unusual and pretty specific to the PHY. I would also have expected pull resistors but the way it's done is to connect one pin to another at reset and disconnect them later on so that both can be used for the intended function (PTP clock and LED). I hope this clarifies our situation a bit. Cheers, Paul -- Paul Kocialkowski, Bootlin Embedded Linux and kernel engineering https://bootlin.com