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[75.72.117.212]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8b53c0e7d3esm83413106d6.28.2026.05.02.19.22.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 02 May 2026 19:22:41 -0700 (PDT) Message-ID: <5d18fabb-aac8-4a3a-ae2d-85eaf18cd4ee@riscstar.com> Date: Sat, 2 May 2026 21:22:37 -0500 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next 08/12] dt-bindings: net: toshiba,tc965x-dwmac: add TC956x Ethernet bridge To: Andrew Lunn Cc: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, maxime.chevallier@bootlin.com, rmk+kernel@armlinux.org.uk, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linusw@kernel.org, brgl@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, Daniel Thompson , mohd.anwar@oss.qualcomm.com, a0987203069@gmail.com, alexandre.torgue@foss.st.com, ast@kernel.org, boon.khai.ng@altera.com, chenchuangyu@xiaomi.com, chenhuacai@kernel.org, daniel@iogearbox.net, hawk@kernel.org, hkallweit1@gmail.com, inochiama@gmail.com, john.fastabend@gmail.com, julianbraha@gmail.com, livelycarpet87@gmail.com, matthew.gerlach@altera.com, mcoquelin.stm32@gmail.com, me@ziyao.cc, prabhakar.mahadev-lad.rj@bp.renesas.com, richardcochran@gmail.com, rohan.g.thomas@altera.com, sdf@fomichev.me, siyanteng@cqsoftware.com.cn, weishangjuan@eswincomputing.com, wens@kernel.org, netdev@vger.kernel.org, bpf@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260501155421.3329862-1-elder@riscstar.com> <20260501155421.3329862-9-elder@riscstar.com> <1f34cbce-e2dd-4e80-b136-55d0efa50002@lunn.ch> Content-Language: en-US From: Alex Elder In-Reply-To: <1f34cbce-e2dd-4e80-b136-55d0efa50002@lunn.ch> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 5/1/26 12:38 PM, Andrew Lunn wrote: > Your ASCII art of the chip might be useful here as documentation. > >> + # We can't allOf reference Ethernet-controller.yaml because we end up with >> + # contradictory $nodename rules (`ethernet@` versus `pci@`). Happily only a >> + # small number of the properties are useful on TC956x so we can just reference >> + # what we need. > > Why not add an subnodes for the ethernet interfaces? I'm going to wait to respond to this until I've had a chance to discuss it with Daniel. (It might be Tuesday.) > >> +examples: >> + - | >> + pcie { >> + #address-cells = <3>; >> + #size-cells = <2>; >> + >> + tc956x_emac0: pci@0,0 { >> + compatible = "pci1179,0220"; >> + reg = <0x50000 0x0 0x0 0x0 0x0>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + device_type = "pci"; >> + ranges; >> + >> + gpio-controller; >> + #gpio-cells = <2>; > > I've not got to the GPIO driver patch yet... > > Is the GPIO part of the ethernet device, or part of the chip? The > hierarchy here should match the hierarchy of the hardware. The GPIO is part of the TC9564 chip, and is a separate IP within it. Within this chip there is one GPIO controller (as well as a UART and so on), independent of the eMACs. >> + phy-mode = "10gbase-r"; >> + phy-handle = <&tc956x_emac0_phy>; >> + >> + mdio { >> + compatible = "snps,dwmac-mdio"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + tc956x_emac0_phy: ethernet-phy@1c { >> + compatible = "ethernet-phy-id311c.1c12"; >> + reg = <0x1c>; >> + }; >> + }; >> + }; >> + pci@0,1 { >> + compatible = "pci1179,0220"; >> + reg = <0x50100 0x0 0x0 0x0 0x0>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + device_type = "pci"; >> + ranges; >> + > > You second ethernet does not have a gpio controller? Basically, no. We made the decision to create a "chip" abstraction that is responsible for managing these other shared IP blocks (of which only the GPIO controller has a separate driver). Both of the PCIe endpoints are able to manipulate the registers for the GPIO, but we made it the responsibility of function 0--not function 1--to handle that. It's possible that some platforms won't use the built-in GPIO controller to manage PHY resets. So we used this property to signal that it was required. So *if* the gpio-controller (and #gpio-cells) property is present, then function 0 creates an auxiliary device for the GPIO controller. Otherwise something else supplies the GPIO lines managing PHY resets. -Alex > > Andrew