From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A43CC11F67 for ; Tue, 29 Jun 2021 19:32:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7EEBE61DF2 for ; Tue, 29 Jun 2021 19:32:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235135AbhF2Tes convert rfc822-to-8bit (ORCPT ); Tue, 29 Jun 2021 15:34:48 -0400 Received: from mga03.intel.com ([134.134.136.65]:27002 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235252AbhF2Tem (ORCPT ); Tue, 29 Jun 2021 15:34:42 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10030"; a="208262025" X-IronPort-AV: E=Sophos;i="5.83,309,1616482800"; d="scan'208";a="208262025" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2021 12:32:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,309,1616482800"; d="scan'208";a="408546482" Received: from orsmsx606.amr.corp.intel.com ([10.22.229.19]) by orsmga003.jf.intel.com with ESMTP; 29 Jun 2021 12:32:10 -0700 Received: from orsmsx610.amr.corp.intel.com (10.22.229.23) by ORSMSX606.amr.corp.intel.com (10.22.229.19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.4; Tue, 29 Jun 2021 12:32:10 -0700 Received: from orsmsx610.amr.corp.intel.com (10.22.229.23) by ORSMSX610.amr.corp.intel.com (10.22.229.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.4; Tue, 29 Jun 2021 12:32:10 -0700 Received: from orsmsx610.amr.corp.intel.com ([10.22.229.23]) by ORSMSX610.amr.corp.intel.com ([10.22.229.23]) with mapi id 15.01.2242.008; Tue, 29 Jun 2021 12:32:10 -0700 From: "Keller, Jacob E" To: Richard Cochran , "Nguyen, Anthony L" CC: "davem@davemloft.net" , "kuba@kernel.org" , "Machnikowski, Maciej" , "netdev@vger.kernel.org" Subject: RE: [PATCH net-next 2/5] ice: add support for auxiliary input/output pins Thread-Topic: [PATCH net-next 2/5] ice: add support for auxiliary input/output pins Thread-Index: AQHXafOQsu1unZMWWk2FI7QX5ZbbUasmyVGAgANBEXCAAVrXAIAAAYTA Date: Tue, 29 Jun 2021 19:32:09 +0000 Message-ID: <5e60e10f4d5c43b78c9a46834a836cc1@intel.com> References: <20210625185733.1848704-1-anthony.l.nguyen@intel.com> <20210625185733.1848704-3-anthony.l.nguyen@intel.com> <20210626140245.GA15724@hoboy.vegasvil.org> <30480e4a473146f5a38e83e0602bd36c@intel.com> In-Reply-To: <30480e4a473146f5a38e83e0602bd36c@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 x-originating-ip: [10.22.254.132] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org > -----Original Message----- > From: Keller, Jacob E > Sent: Tuesday, June 29, 2021 12:29 PM > To: Keller, Jacob E ; Richard Cochran > ; Nguyen, Anthony L > > Cc: davem@davemloft.net; kuba@kernel.org; Machnikowski, Maciej > ; netdev@vger.kernel.org > Subject: RE: [PATCH net-next 2/5] ice: add support for auxiliary input/output pins > > > > > -----Original Message----- > > From: Keller, Jacob E > > Sent: Monday, June 28, 2021 3:46 PM > > To: Richard Cochran ; Nguyen, Anthony L > > > > Cc: davem@davemloft.net; kuba@kernel.org; Machnikowski, Maciej > > ; netdev@vger.kernel.org > > Subject: RE: [PATCH net-next 2/5] ice: add support for auxiliary input/output > pins > > > > > > > > > -----Original Message----- > > > From: Richard Cochran > > > Sent: Saturday, June 26, 2021 7:03 AM > > > To: Nguyen, Anthony L > > > Cc: davem@davemloft.net; kuba@kernel.org; Machnikowski, Maciej > > > ; netdev@vger.kernel.org; Keller, Jacob E > > > > > > Subject: Re: [PATCH net-next 2/5] ice: add support for auxiliary input/output > > pins > > > > > > On Fri, Jun 25, 2021 at 11:57:30AM -0700, Tony Nguyen wrote: > > > > > > > @@ -783,6 +1064,17 @@ static long ice_ptp_create_clock(struct ice_pf *pf) > > > > info = &pf->ptp.info; > > > > dev = ice_pf_to_dev(pf); > > > > > > > > + /* Allocate memory for kernel pins interface */ > > > > + if (info->n_pins) { > > > > + info->pin_config = devm_kcalloc(dev, info->n_pins, > > > > + sizeof(*info->pin_config), > > > > + GFP_KERNEL); > > > > + if (!info->pin_config) { > > > > + info->n_pins = 0; > > > > + return -ENOMEM; > > > > + } > > > > + } > > > > > > How is this supposed to worK? > > > > > > - If n_pins is non-zero, there must also be a ptp_caps.verify method, > > > but you don't provide one. > > > > > > > Hmm. Yea, that's missing. > > Ok, turns out this is only intended for a later patch that adds support for some > pins on E810-T devices, but that work wasn't done yet. We need to split this up > more, but currently we never set info->n_pins > 0 so this is effectively dead code. > > For now, we need to drop this patch from the series. Looks like this was pulled already. It shouldn't cause an issue because n_pins is never set to non-zero so it's really just dead code until we can complete the E810-T work. Thanks, Jake