From mboxrd@z Thu Jan  1 00:00:00 1970
From: Michal Simek <michal.simek@xilinx.com>
Subject: Re: [PATCH] net: phy: Fix mask value write on gmii2rgmii converter
 speed register.
Date: Fri, 15 Sep 2017 09:49:41 +0200
Message-ID: <5f4bd003-d251-5a14-497a-9cc72dd0f160@xilinx.com>
References: <1505373391-18697-1-git-send-email-fahad.kunnathadi@dexceldesigns.com>
 <20170914143454.GB27601@lunn.ch>
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Cc: <f.fainelli@gmail.com>, <netdev@vger.kernel.org>,
        <michal.simek@xilinx.com>, <linux-kernel@vger.kernel.org>,
        <soren.brinkmann@xilinx.com>,
        <linux-arm-kernel@lists.infradead.org>
To: Andrew Lunn <andrew@lunn.ch>,
        Fahad Kunnathadi <fahad.kunnathadi@dexceldesigns.com>
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On 14.9.2017 16:34, Andrew Lunn wrote:
> On Thu, Sep 14, 2017 at 12:46:31PM +0530, Fahad Kunnathadi wrote:
>> To clear Speed Selection in MDIO control register(0x10),
>> ie, clear bits 6 and 13 to zero while keeping other bits same.
>> Before AND operation,The Mask value has to be perform with bitwise NOT
>> operation (ie, ~ operator)
>>
>> This patch clears current speed selection before writing the
>> new speed settings to gmii2rgmii converter
> 
> Hi Fahad
> 
> I expect you will find other issues with this driver. I pointed some
> out at the time it is submitted, but the developers went quiet as soon
> as it was accepted.

Can you please point me to that email?
I will create ticket about it in our system to get them resolved.

Thanks,
Michal