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[2003:ea:8f1c:1800:8cc6:804e:b81b:aa56]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47d7f6f0e15sm258461215e9.10.2026.01.10.06.59.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 10 Jan 2026 06:59:18 -0800 (PST) Message-ID: <5f5410fc-51c0-42cd-8034-5122d8fa762a@gmail.com> Date: Sat, 10 Jan 2026 15:59:16 +0100 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next 1/2] net: phy: realtek: add PHY driver for RTL8127ATF To: Daniel Golle , Fabio Baltieri Cc: Andrew Lunn , Andrew Lunn , Russell King - ARM Linux , Paolo Abeni , Eric Dumazet , David Miller , Jakub Kicinski , Vladimir Oltean , Michael Klein , Realtek linux nic maintainers , Aleksander Jan Bajkowski , "netdev@vger.kernel.org" References: <52011433-79d3-4097-a2d3-d1cca1f66acb@gmail.com> <492763d9-9ece-41a1-a542-d09d9b77ab4a@gmail.com> Content-Language: en-US From: Heiner Kallweit In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 1/9/2026 2:26 AM, Daniel Golle wrote: > On Thu, Jan 08, 2026 at 11:20:21PM +0000, Fabio Baltieri wrote: >> On Thu, Jan 08, 2026 at 10:56:14PM +0000, Daniel Golle wrote: >>>> +static int rtlgen_sfp_read_status(struct phy_device *phydev) >>>> +{ >>>> + int val, err; >>>> + >>>> + err = genphy_update_link(phydev); >>>> + if (err) >>>> + return err; >>>> + >>>> + if (!phydev->link) >>>> + return 0; >>>> + >>>> + val = rtlgen_read_vend2(phydev, RTL_VND2_PHYSR); >>> I'll leave it like that for now when sending v2 of this series. Then you can covert it to phy_read(phydev, RTL_PHYSR) as part of your series. >>> This should be the same as >>> phy_read(phydev, MII_RESV2); /* on page 0 */ >>> Please try. >> >> Tried it on my setup, the two calls do indeed seem to return the same >> value. > > Thank you for confirming that. > > My understanding at this point is that only register 0x10 to 0x17 are > actually paged (ie. the 3 bits of freedom in the > RTL822X_VND2_TO_PAGE_REG apply to all pages), and that seems to apply for > all 1G, 2.5G and 5G (and 10G?) RealTek PHYs. > > Hence we do not need to use paged register access for register 0x0...0xf > and 0x18..0x1e. And the paged operations we do have there right now can > all be described as registers on MDIO_MMD_VEND2. And maybe that's what > we should do then, implementing .read_mmd and .write_mmd similar to > rtl822xb_read_mmd and rtl822xb_write_mmd for all PHYs, with the only > difference that for older PHYs all MMDs other than MDIO_MMD_VEND2 have > to be emulated similar to rtlgen_read_mmd and rtl822x_read_mmd. > > The current way we access MDIO_MMD_VEND2 on older PHYs also also fishy > as it depends on __mdiobus_c45_read as well as the PHY listening to the > broadcast address 0: Especially for 1GE PHYs not all MDIO controllers > are capable of Clause-45 access, and listening on address 0 works (at > best) if there is only one PHY in the bus doing that, and it can be > disabled via BIT(13) on PHYCR1. For internal PHYs of PCIe NICs this is > fine, of course, but for standalone PHYs not really. > > tl;dr: drivers/net/phy/realtek/ has signed up for some serious > weight-loss program.