From: Andrew Lunn <andrew@lunn.ch>
To: Srinivas Neeli <srinivas.neeli@amd.com>
Cc: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com,
kuba@kernel.org, pabeni@redhat.com, michal.simek@amd.com,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
richardcochran@gmail.com, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, git@amd.com
Subject: Re: [RFC PATCH 0/8] xilinx: tsn: Add TSN Endpoint Ethernet MAC driver support
Date: Thu, 19 Feb 2026 17:42:56 +0100 [thread overview]
Message-ID: <5f884e29-151a-4ee7-9e1a-d7e1f84d9f6c@lunn.ch> (raw)
In-Reply-To: <20260219054911.2017362-1-srinivas.neeli@amd.com>
On Thu, Feb 19, 2026 at 11:19:03AM +0530, Srinivas Neeli wrote:
> Introduce a new network driver for the AMD LogiCORE 100M/1G TSN
> Subsystem IP, also known as the TSN Endpoint Ethernet MAC, which
> implements IEEE 802.1 Time-Sensitive Networking (TSN) features for
> deterministic and low-latency Ethernet communication in real-time and
> industrial automation use cases.
>
> IP Core Overview:
> The AMD LogiCORE 100M/1G TSN Subsystem IP solution (named as TSN Endpoint
> Ethernet MAC IP in the IP catalog) implements IEEE 802.1 Time Sensitive
> Networking (TSN) Standards and provides a low latency Bridged Endpoint or
> Endpoint only solutions.
So an Endpoint only solution is not connected to the switch? It
outputs RGMII, can have a PHY connected to it, and so is a single
netdev interface? You would typically use this in a client?
But you can also instantiate the same MAC multiple times, connected to
an Ethernet switch? That would be the bridged endpoint?
> The bridged endpoint solution consists of a 3-port
> switch that connects to an endpoint including Linux software drivers. For
> Bridged Endpoint (Switch Endpoint), two ports connects to the network and
> one port connects to an internal Endpoint.
To the host, does the internal endpoint just look like a standard
netdev?
What i'm trying to do is get an answer to: Is this a DSA switch, or a
pure switchdev switch. If the host sees a netdev which is connected to
a port of the switch, it is probably a DSA switch. If the host only
sees the user ports, it is probably a pure switchdev switch.
> It supports the use of
> GMII/RGMII interfaces connecting to a physical-side interface (PHY) chip
> with full duplex 100 Mb/s and 1 Gb/s operations.
No 10Mbps support?
> - Provides feature rich Ethernet Switch that caters to various network
> needs
> * 3-port Switch (2-external, 1-internal)
> * Programmable cut-through and store-forward operations
> * 4-port Switch (2-external, 2-internal) extension through
> 'Endpoint Extension' and 'Endpoint Packet Switching' features
Why not N-ports? Is it really set to 3 or 4? It cannot be synthesised
for 5, 8?
> Sample hardware architecture diagram for Bidge End Point like below:
>
> +------------------+
> | MCDMA |
> +---------+--------+
> Q0---Q7
> |
> +------------------------------------------------------------ +
> | | TSN sub system(Bridge End Point) |
> | | |
> | +------+----+ Port 0 +-----------------------+ |
> | | EndPoint |<--------->| TSN Switch | |
> | | (EP) | +----+-------------+----+ |
> | +-----------+ | | |
> | | | |
> | Port 1 Port 2 |
> | | | |
> | +-----------+ +-----------+ |
> | | MAC-1 | | MAC-2 | |
> | | (ETH1) | | (ETH2) | |
> | +-----+-----+ +-----+-----+ |
> | | | |
> | | | |
> +-------------------------------------------------------------+
> | |
> RGMII RGMII
> | |
> +-----------+ +-----------+
> | PHY1 | | PHY2 |
> | (Port 0) | | (Port 2) |
> +-----------+ +-----------+
>
So how does the host send a frame out Port 2? Is there an extra header
on the frame sent by EndPoint, which the switch interprets?
FYI: Seems like PHY1 (port 0) is a typO.
> - During driver initialization, all switch ports (Endpoint, MAC1, MAC2)
> are configured into the Forwarding state to enable data flow across the
> fabric.
Which is wrong. The Linux model is that switch ports are just
netdevs. You configure them just like every other netdev in the
system. Newly created netdevs are standalone. They only allow frames
to pass between the wire and the host. If you want them to L2 forwards
frames between ports you need to add them to a bridge.
Andrew
next prev parent reply other threads:[~2026-02-19 16:43 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-19 5:49 [RFC PATCH 0/8] xilinx: tsn: Add TSN Endpoint Ethernet MAC driver support Srinivas Neeli
2026-02-19 5:49 ` [RFC PATCH 1/8] dt-bindings: net: Add TSN Endpoint Ethernet MAC support Srinivas Neeli
2026-02-19 16:53 ` Andrew Lunn
2026-02-20 13:03 ` Neeli, Srinivas
2026-02-20 13:39 ` Andrew Lunn
2026-02-24 11:08 ` Neeli, Srinivas
2026-02-19 5:49 ` [RFC PATCH 2/8] net: xilinx: tsn: Introduce TSN core driver skeleton Srinivas Neeli
2026-02-19 7:32 ` Krzysztof Kozlowski
2026-02-19 5:49 ` [RFC PATCH 3/8] net: xilinx: tsn: Add TSN endpoint and MCDMA support Srinivas Neeli
2026-02-19 5:49 ` [RFC PATCH 4/8] xilinx: tsn: Add Ethernet MAC (EMAC) and MDIO support to the TSN driver Srinivas Neeli
2026-02-19 17:05 ` Andrew Lunn
2026-02-20 13:08 ` Neeli, Srinivas
2026-02-20 15:03 ` Andrew Lunn
2026-02-24 11:11 ` Neeli, Srinivas
2026-02-20 15:12 ` Andrew Lunn
2026-02-24 11:15 ` Neeli, Srinivas
2026-02-19 5:49 ` [RFC PATCH 5/8] net: xilinx: tsn: Add TSN switch support with port state and frame filter control Srinivas Neeli
2026-02-19 5:49 ` [RFC PATCH 6/8] dt-bindings: net: Add PTP interrupt support Srinivas Neeli
2026-02-20 15:17 ` Andrew Lunn
2026-02-19 5:49 ` [RFC PATCH 7/8] net: xilinx: tsn: Add PTP hardware clock (PHC) and timer support Srinivas Neeli
2026-02-19 5:49 ` [RFC PATCH 8/8] net: xilinx: tsn: Add PTP packet transmission support Srinivas Neeli
2026-02-19 7:34 ` [RFC PATCH 0/8] xilinx: tsn: Add TSN Endpoint Ethernet MAC driver support Krzysztof Kozlowski
2026-02-19 16:42 ` Andrew Lunn [this message]
2026-02-20 12:59 ` Neeli, Srinivas
2026-02-20 13:36 ` Andrew Lunn
2026-03-05 11:46 ` Neeli, Srinivas
2026-03-26 10:11 ` Neeli, Srinivas
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