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(93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.gmail.com with ESMTPSA id de37sm4601824ejc.60.2021.12.12.09.43.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Dec 2021 09:43:38 -0800 (PST) Message-ID: <61b634ca.1c69fb81.ebe5f.24cf@mx.google.com> X-Google-Original-Message-ID: Date: Sun, 12 Dec 2021 18:43:35 +0100 From: Ansuel Smith To: Florian Fainelli Cc: Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: Re: [net-next RFC PATCH v4 15/15] net: dsa: qca8k: cache lo and hi for mdio write References: <20211211195758.28962-1-ansuelsmth@gmail.com> <20211211195758.28962-16-ansuelsmth@gmail.com> <8ceaa6c1-9840-17b4-73f8-1a7f665e430f@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <8ceaa6c1-9840-17b4-73f8-1a7f665e430f@gmail.com> Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Sat, Dec 11, 2021 at 08:04:42PM -0800, Florian Fainelli wrote: > > > On 12/11/2021 11:57 AM, Ansuel Smith wrote: > > From Documentation, we can cache lo and hi the same way we do with the > > page. This massively reduce the mdio write as 3/4 of the time we only > > require to write the lo or hi part for a mdio write. > > > > Signed-off-by: Ansuel Smith > > --- > > drivers/net/dsa/qca8k.c | 49 ++++++++++++++++++++++++++++++++++++----- > > 1 file changed, 44 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c > > index 375a1d34e46f..b109a74031c6 100644 > > --- a/drivers/net/dsa/qca8k.c > > +++ b/drivers/net/dsa/qca8k.c > > @@ -94,6 +94,48 @@ qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page) > > *page = regaddr & 0x3ff; > > } > > +static u16 qca8k_current_lo = 0xffff; > > Let's assume I have two qca8k switches in my system on the same or a > different MDIO bus, is not the caching supposed to be a per-qca8k switch > instance thing? > Also another user made me notice this... This problem is present from when the driver was implemented and I think with the assumption that only one switch was present in the device. We actually found SoC with 2 qca8k switch. I will add a patch to move these stuff (and the cache page variable) in the qca8k priv. > > + > > +static int > > +qca8k_set_lo(struct mii_bus *bus, int phy_id, u32 regnum, u16 lo) > > +{ > > + int ret; > > + > > + if (lo == qca8k_current_lo) { > > + // pr_info("SAME LOW"); > > Stray debugging left. > Sorry. > > + return 0; > > + } > > + > > + ret = bus->write(bus, phy_id, regnum, lo); > > + if (ret < 0) > > + dev_err_ratelimited(&bus->dev, > > + "failed to write qca8k 32bit lo register\n"); > > + > > + qca8k_current_lo = lo; > > + return 0; > > +} > > + > > +static u16 qca8k_current_hi = 0xffff; > > + > > +static int > > +qca8k_set_hi(struct mii_bus *bus, int phy_id, u32 regnum, u16 hi) > > +{ > > + int ret; > > + > > + if (hi == qca8k_current_hi) { > > + // pr_info("SAME HI"); > > Likewise > -- > Florian -- Ansuel