From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57277C169C4 for ; Fri, 8 Feb 2019 10:25:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 14619206A3 for ; Fri, 8 Feb 2019 10:25:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="YY+xV2/0" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726645AbfBHKZO (ORCPT ); Fri, 8 Feb 2019 05:25:14 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:41170 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726081AbfBHKZO (ORCPT ); Fri, 8 Feb 2019 05:25:14 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x18AOsDK108349; Fri, 8 Feb 2019 04:24:54 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1549621494; bh=GkYySERVFS8yENN1b7siZyNRSut0IDZpDyr82F0NTdg=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=YY+xV2/0ftLKiTCKwVdtaI3iDlzbTO2ZWwL8tvf8zgGegfBQSO4aXPigg530mzEML JgwE8ojj2IMTP+aXlk4XDyH+4AarPxbQM0dgvalyqjIQpM1AtM08/n9jZ+pytRQHub pOcYSwkfn+/Q85ua7g2WnG5LA0hYHPobK0LFxhcA= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x18AOrjw045141 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 8 Feb 2019 04:24:53 -0600 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Fri, 8 Feb 2019 04:24:53 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Fri, 8 Feb 2019 04:24:53 -0600 Received: from [172.24.190.233] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x18AOn0h026284; Fri, 8 Feb 2019 04:24:51 -0600 Subject: Re: [PATCH net-next v2 2/6] phy: armada38x: add common phy support To: Russell King , Andrew Lunn , Gregory Clement , Jason Cooper , Sebastian Hesselbarth , Thomas Petazzoni CC: , , References: <20190207161825.ueinmyf6ygjiqzzy@shell.armlinux.org.uk> From: Kishon Vijay Abraham I Message-ID: <638c9c62-6b26-e1d8-1e05-50d5367c7c40@ti.com> Date: Fri, 8 Feb 2019 15:54:17 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On 07/02/19 9:49 PM, Russell King wrote: > Add support for the Armada 38x common phy to allow us to change the > speed of the Ethernet serdes lane. This driver only supports > manipulation of the speed, it does not support configuration of the > common phy. > > Signed-off-by: Russell King This patch will conflict with PHY pull request (in the marvell Kconfig and Makefile). But the resolution should be trivial and should be okay to go via -net tree. FWIW Acked-by: Kishon Vijay Abraham I > --- > drivers/phy/marvell/Kconfig | 10 ++ > drivers/phy/marvell/Makefile | 1 + > drivers/phy/marvell/phy-armada38x-comphy.c | 237 +++++++++++++++++++++++++++++ > 3 files changed, 248 insertions(+) > create mode 100644 drivers/phy/marvell/phy-armada38x-comphy.c > > diff --git a/drivers/phy/marvell/Kconfig b/drivers/phy/marvell/Kconfig > index 6fb4b56e4c14..224ea4e6a46d 100644 > --- a/drivers/phy/marvell/Kconfig > +++ b/drivers/phy/marvell/Kconfig > @@ -21,6 +21,16 @@ config PHY_BERLIN_USB > help > Enable this to support the USB PHY on Marvell Berlin SoCs. > > +config PHY_MVEBU_A38X_COMPHY > + tristate "Marvell Armada 38x comphy driver" > + depends on ARCH_MVEBU || COMPILE_TEST > + depends on OF > + select GENERIC_PHY > + help > + This driver allows to control the comphy, an hardware block providing > + shared serdes PHYs on Marvell Armada 38x. Its serdes lanes can be > + used by various controllers (Ethernet, sata, usb, PCIe...). > + > config PHY_MVEBU_CP110_COMPHY > tristate "Marvell CP110 comphy driver" > depends on ARCH_MVEBU || COMPILE_TEST > diff --git a/drivers/phy/marvell/Makefile b/drivers/phy/marvell/Makefile > index 3975b144f8ec..59b6c03ef756 100644 > --- a/drivers/phy/marvell/Makefile > +++ b/drivers/phy/marvell/Makefile > @@ -2,6 +2,7 @@ > obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY) += phy-armada375-usb2.o > obj-$(CONFIG_PHY_BERLIN_SATA) += phy-berlin-sata.o > obj-$(CONFIG_PHY_BERLIN_USB) += phy-berlin-usb.o > +obj-$(CONFIG_PHY_MVEBU_A38X_COMPHY) += phy-armada38x-comphy.o > obj-$(CONFIG_PHY_MVEBU_CP110_COMPHY) += phy-mvebu-cp110-comphy.o > obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o > obj-$(CONFIG_PHY_PXA_28NM_HSIC) += phy-pxa-28nm-hsic.o > diff --git a/drivers/phy/marvell/phy-armada38x-comphy.c b/drivers/phy/marvell/phy-armada38x-comphy.c > new file mode 100644 > index 000000000000..3e00bc679d4e > --- /dev/null > +++ b/drivers/phy/marvell/phy-armada38x-comphy.c > @@ -0,0 +1,237 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2018 Russell King, Deep Blue Solutions Ltd. > + * > + * Partly derived from CP110 comphy driver by Antoine Tenart > + * > + */ > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define MAX_A38X_COMPHY 6 > +#define MAX_A38X_PORTS 3 > + > +#define COMPHY_CFG1 0x00 > +#define COMPHY_CFG1_GEN_TX(x) ((x) << 26) > +#define COMPHY_CFG1_GEN_TX_MSK COMPHY_CFG1_GEN_TX(15) > +#define COMPHY_CFG1_GEN_RX(x) ((x) << 22) > +#define COMPHY_CFG1_GEN_RX_MSK COMPHY_CFG1_GEN_RX(15) > +#define GEN_SGMII_1_25GBPS 6 > +#define GEN_SGMII_3_125GBPS 8 > + > +#define COMPHY_STAT1 0x18 > +#define COMPHY_STAT1_PLL_RDY_TX BIT(3) > +#define COMPHY_STAT1_PLL_RDY_RX BIT(2) > + > +#define COMPHY_SELECTOR 0xfc > + > +struct a38x_comphy; > + > +struct a38x_comphy_lane { > + void __iomem *base; > + struct a38x_comphy *priv; > + unsigned int n; > + > + int port; > +}; > + > +struct a38x_comphy { > + void __iomem *base; > + struct device *dev; > + struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; > +}; > + > +static const u8 gbe_mux[MAX_A38X_COMPHY][MAX_A38X_PORTS] = { > + { 0, 0, 0 }, > + { 4, 5, 0 }, > + { 0, 4, 0 }, > + { 0, 0, 4 }, > + { 0, 3, 0 }, > + { 0, 0, 3 }, > +}; > + > +static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane, > + unsigned int offset, u32 mask, u32 value) > +{ > + u32 val; > + > + val = readl_relaxed(lane->base + offset) & ~mask; > + writel(val | value, lane->base + offset); > +} > + > +static void a38x_comphy_set_speed(struct a38x_comphy_lane *lane, > + unsigned int gen_tx, unsigned int gen_rx) > +{ > + a38x_comphy_set_reg(lane, COMPHY_CFG1, > + COMPHY_CFG1_GEN_TX_MSK | COMPHY_CFG1_GEN_RX_MSK, > + COMPHY_CFG1_GEN_TX(gen_tx) | > + COMPHY_CFG1_GEN_RX(gen_rx)); > +} > + > +static int a38x_comphy_poll(struct a38x_comphy_lane *lane, > + unsigned int offset, u32 mask, u32 value) > +{ > + u32 val; > + int ret; > + > + ret = readl_relaxed_poll_timeout_atomic(lane->base + offset, val, > + (val & mask) == value, > + 1000, 150000); > + > + if (ret) > + dev_err(lane->priv->dev, > + "comphy%u: timed out waiting for status\n", lane->n); > + > + return ret; > +} > + > +/* > + * We only support changing the speed for comphys configured for GBE. > + * Since that is all we do, we only poll for PLL ready status. > + */ > +static int a38x_comphy_set_mode(struct phy *phy, enum phy_mode mode, int sub) > +{ > + struct a38x_comphy_lane *lane = phy_get_drvdata(phy); > + unsigned int gen; > + > + if (mode != PHY_MODE_ETHERNET) > + return -EINVAL; > + > + switch (sub) { > + case PHY_INTERFACE_MODE_SGMII: > + case PHY_INTERFACE_MODE_1000BASEX: > + gen = GEN_SGMII_1_25GBPS; > + break; > + > + case PHY_INTERFACE_MODE_2500BASEX: > + gen = GEN_SGMII_3_125GBPS; > + break; > + > + default: > + return -EINVAL; > + } > + > + a38x_comphy_set_speed(lane, gen, gen); > + > + return a38x_comphy_poll(lane, COMPHY_STAT1, > + COMPHY_STAT1_PLL_RDY_TX | > + COMPHY_STAT1_PLL_RDY_RX, > + COMPHY_STAT1_PLL_RDY_TX | > + COMPHY_STAT1_PLL_RDY_RX); > +} > + > +static const struct phy_ops a38x_comphy_ops = { > + .set_mode = a38x_comphy_set_mode, > + .owner = THIS_MODULE, > +}; > + > +static struct phy *a38x_comphy_xlate(struct device *dev, > + struct of_phandle_args *args) > +{ > + struct a38x_comphy_lane *lane; > + struct phy *phy; > + u32 val; > + > + if (WARN_ON(args->args[0] >= MAX_A38X_PORTS)) > + return ERR_PTR(-EINVAL); > + > + phy = of_phy_simple_xlate(dev, args); > + if (IS_ERR(phy)) > + return phy; > + > + lane = phy_get_drvdata(phy); > + if (lane->port >= 0) > + return ERR_PTR(-EBUSY); > + > + lane->port = args->args[0]; > + > + val = readl_relaxed(lane->priv->base + COMPHY_SELECTOR); > + val = (val >> (4 * lane->n)) & 0xf; > + > + if (!gbe_mux[lane->n][lane->port] || > + val != gbe_mux[lane->n][lane->port]) { > + dev_warn(lane->priv->dev, > + "comphy%u: not configured for GBE\n", lane->n); > + phy = ERR_PTR(-EINVAL); > + } > + > + return phy; > +} > + > +static int a38x_comphy_probe(struct platform_device *pdev) > +{ > + struct phy_provider *provider; > + struct device_node *child; > + struct a38x_comphy *priv; > + struct resource *res; > + void __iomem *base; > + > + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + base = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(base)) > + return PTR_ERR(base); > + > + priv->dev = &pdev->dev; > + priv->base = base; > + > + for_each_available_child_of_node(pdev->dev.of_node, child) { > + struct phy *phy; > + int ret; > + u32 val; > + > + ret = of_property_read_u32(child, "reg", &val); > + if (ret < 0) { > + dev_err(&pdev->dev, "missing 'reg' property (%d)\n", > + ret); > + continue; > + } > + > + if (val >= MAX_A38X_COMPHY || priv->lane[val].base) { > + dev_err(&pdev->dev, "invalid 'reg' property\n"); > + continue; > + } > + > + phy = devm_phy_create(&pdev->dev, child, &a38x_comphy_ops); > + if (IS_ERR(phy)) > + return PTR_ERR(phy); > + > + priv->lane[val].base = base + 0x28 * val; > + priv->lane[val].priv = priv; > + priv->lane[val].n = val; > + priv->lane[val].port = -1; > + phy_set_drvdata(phy, &priv->lane[val]); > + } > + > + dev_set_drvdata(&pdev->dev, priv); > + > + provider = devm_of_phy_provider_register(&pdev->dev, a38x_comphy_xlate); > + > + return PTR_ERR_OR_ZERO(provider); > +} > + > +static const struct of_device_id a38x_comphy_of_match_table[] = { > + { .compatible = "marvell,armada-380-comphy" }, > + { }, > +}; > +MODULE_DEVICE_TABLE(of, a38x_comphy_of_match_table); > + > +static struct platform_driver a38x_comphy_driver = { > + .probe = a38x_comphy_probe, > + .driver = { > + .name = "armada-38x-comphy", > + .of_match_table = a38x_comphy_of_match_table, > + }, > +}; > +module_platform_driver(a38x_comphy_driver); > + > +MODULE_AUTHOR("Russell King "); > +MODULE_DESCRIPTION("Common PHY driver for Armada 38x SoCs"); > +MODULE_LICENSE("GPL v2"); >