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X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 08:11:12.2169 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f78f0cde-f370-45e2-5202-08ddfa78c28e X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.44];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF00028D06.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR10MB3331 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTIwMDAwMSBTYWx0ZWRfX7ko80snAg5Y2 qaW30j3YWnjbw4Lu0VfAoJz4yAhy3+llQBHCK/SOBQycRNg5o/y3M48ulb2dVH8XwzlHkWF6iUJ i9bUpVZXJJSZsw+5cAermcHfc7XmkOBlpVmccp+sVTQd+OH3rt6exDr18nA2ene9jsKYcXO9Fht GXj0NbKPjM2d5dg+ujqJ7hjBT5KKQWz6vuoT9Cyc4Gtk3rshybNWGEeFdQkBepHNJCV0mDeestK i1U3yXP2aiZVQKHtUTr+t2I4++HjT50bajbaC+4b9efw4T4+n5GOHriHYDVIoRUk/QNRcBS9XR1 vPXXy+M0FWdFy4xsOk7lWMyhogSIQNrmORIUTQRip2PwL/vNymt1NbacBB9pCvJD6P1HfM+qGhk I1/2TA4p X-Proofpoint-ORIG-GUID: knBOxXk71hxkGghKZMY8jplHdGT31BuC X-Authority-Analysis: v=2.4 cv=PLMP+eqC c=1 sm=1 tr=0 ts=68d25623 cx=c_pps a=r3amAyZnyFs1+HRFMa/lSA==:117 a=Tm9wYGWyy1fMlzdxM1lUeQ==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=h8e1o3o8w34MuCiiGQrqVE4VwXA=:19 a=wKuvFiaSGQ0qltdbU6+NXLB8nM8=:19 a=Ol13hO9ccFRV9qXi2t6ftBPywas=:19 a=ei1tl_lDKmQA:10 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=s63m1ICgrNkA:10 a=KrXZwBdWH7kA:10 a=NQGlzXKa162JxgxB1IUA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-GUID: knBOxXk71hxkGghKZMY8jplHdGT31BuC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-23_01,2025-09-22_05,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 malwarescore=0 suspectscore=0 bulkscore=0 phishscore=0 priorityscore=1501 spamscore=0 impostorscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509200001 On 9/18/25 17:36, Russell King (Oracle) wrote: > On Thu, Sep 18, 2025 at 05:07:00PM +0200, Gatien CHEVALLIER wrote: >> On 9/18/25 15:59, Russell King (Oracle) wrote: >>> > So no. In a situation like this, either we want to be in interrupt >>> mode (in which case we have an interrupt), or the pin is wired to >>> a power management controller and needs to be in PME mode, or it isn't >>> wired. >>> >> >> If you are in interrupt mode, plugging a cable would trigger a >> system wakeup in low-power mode if the INTB/PMEB line is wired to a >> power management controller and the WoL is enabled because we're no >> longer in polling mode, wouldn't it? > > What Andrew suggested, which is what I implemented for Realtek, other > interrupts get disabled when we enter suspend: > > static int rtl8211f_suspend(struct phy_device *phydev) > { > ... > /* If a PME event is enabled, then configure the interrupt for > * PME events only, disabling link interrupt. We avoid switching > * to PMEB mode as we don't have a status bit for that. > */ > if (device_may_wakeup(&phydev->mdio.dev)) { > ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, > RTL8211F_INER_PME); > > This disables all other interrupts when entering suspend _if_ WoL > is enabled and only if WoL is enabled. > > If you're getting woken up when you unplug/replug the ethernet cable > when WoL is disabled, that suggests you have something wrong in your > interrupt controller - the wake-up state of the interrupt is managed > by core driver-model code. I tested this on nVidia Jetson Xavier NX > and if WoL wasn't enabled at the PHY, no wakeup occurred. > I'll replicate what you've done for the masking of interrupt when going to low-power modes to the Microchip driver and see where it takes me. The wakeup occurred because I didn't mask the other interrupt sources in nINT mode... :) >> You can argue that as per the Realtek 8211F datasheet: >> "The interrupts can be individually enabled or disabled by setting or >> clearing bits in the interrupt enable register INER". That requires >> PHY registers handling when going to low-power mode. > > ... which is what my patch does. > >> There are PHYs like the LAN8742 on which 3 pins can be configured >> as nINT(equivalent to INTB), and 2 as nPME(equivalent to PMEB). The >> smsc driver, as is, contains hardcoded nPME mode on the >> LED2/nINT/nPME/nINTSEL pin. What if a manufacturer wired the power >> management controller to the LED1/nINT/nPME/nINTSEL? >> This is where the pinctrl would help even if I do agree it might be a >> bit tedious at first. The pinctrl would be optional though. > > I'm not opposing the idea of pinctrl on PHYs. I'm opposing the idea > of tying it into the WoL code in a way that makes it mandatory. > Of course, if it makes sense for a PHY driver to do pinctrl stuff > then go ahead - and if from that, the driver can work out that > the PHY is wake-up capable, even better. > > What I was trying to say is that in such a case as the Realtek > driver, I don't want to see pinctrl forced upon it unless there is > a real reason and benefit, especially when there are simpler ways > to do this. > Yes, sure, I think there's a proper use-case for it. If it's going to happen, I think it would need a dedicated P-R. I'll send a V3 in the near future addressing what we discussed here. Thank you for the feedback. > I also think that it would be helpful to add the wakeup-source > property where PHYs are so capable even if the PHY driver doesn't > need it for two reasons. 1. OS independence. 2. it's useful docs. > 3. just because our driver as it stands at whatever moment in time > doesn't make use of it doesn't mean that will always be the case. > (e.g., we may want to have e.g. phylib looking at that property.) >