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Mon, 9 Nov 2026 02:30:17 -0800 Message-ID: <64bdfae3-6747-475f-9b90-4882d651d1ee@nvidia.com> Date: Mon, 9 Nov 2026 12:30:14 +0200 X-Mailing-List: netdev@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH rdma-next 20/23] RDMA/mlx5: Clamp log_max_* shifts in QP and WQ limit checks To: CC: , , , , , , , , , , , , , , References: <20261103163949.1554-21-yishaih@nvidia.com> <179408310595.994134.12854233732790224193@kernel.org> Content-Language: en-US From: Yishai Hadas In-Reply-To: <179408310595.994134.12854233732790224193@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002317:EE_|MN0PR12MB5811:EE_ X-MS-Office365-Filtering-Correlation-Id: 5390b833-c15c-42da-61bd-08df3e4c7e67 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|7416014|1800799024|23010399003|82310400026|376014|22082099003|18002099003|10067099003|261009223027099003|56012099006|4143699003|11063799006|261028144727099003|261022105027099003|261026140227099003|261021135927099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: GGEiEvMQTwS8t8FSjtNZjvM2SFScN8daYOs19Eypm3uZawnBbXmxwL88KXAH4o8NCkjFOYi18GdJxQ0S1c2sLa4M2Pttvrwo+2IFrVwFvaRVPXvEE1LqUWFUdgSBi+t3H9hKeL8kB9vFFiZxBSa8qQvi2P1ata8+47jJDe+uaspRKdRdIIpgoUv8IT8sR0JZcghn5J6jTS9TnU+khwGXcitKLSKyU91urfjInOA7keVmuRmwGNNVvmxQukKhLe8r1RrCpgYAoOHN1yP1GbGXbaceuIvnddvSCCRUPINo5H6tYRI31sVdcXfL69ikIM/9Uaqca3yxOVAj1lccidxAItulERigvgW6Qn2FJg5er1qxBSpMh/cNUOwfYEfJJEf/qHsYOIXYpuc2XHJr0jR6fqIsuSRqWn1hkkjLKcpMxLMjXE9dqo1+IYcaGtgUGL9G X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2026 10:30:36.8720 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5390b833-c15c-42da-61bd-08df3e4c7e67 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002317.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5811 On 07/11/2026 22:25, netdev-bot+sashiko@kernel.org wrote: > Thank you for your contribution! Sashiko AI review found more severe > issue(s) in other patches of this series. This mail is only an FYI, in case > you want to address the nit picks below when you respin. > > Low priority / nit picks for your consideration: > > - [Low] The commit message says each limit is computed from "an 8-bit > log_max_* FW capability". > > -- > > RDMA/mlx5: Clamp log_max_* shifts in QP and WQ limit checks > > This commit replaces several open-coded 1 << MLX5_CAP_GEN(...) limit > calculations in drivers/infiniband/hw/mlx5/qp.c with > MLX5_CAP_GEN_LOGSZ_U32(). This avoids an undefined shift when a NIC > reports a log_max_* capability of 31 or more. The affected checks are in > set_rq_size(), calc_sq_size(), set_user_buf_size(), create_dci(), > create_user_qp(), validate_rd_atomic() and set_user_rq_size(). > >> Several QP and WQ size checks in qp.c compute their limit as >> 1 << cap, where cap is an 8-bit log_max_* FW capability. An untrusted >> NIC can report 31 or more, which makes the shift undefined. > > [Severity: Low] > This isn't a bug, but is "an 8-bit log_max_* FW capability" accurate for > all the caps this patch touches? > > In struct mlx5_ifc_cmd_hca_cap_bits in include/linux/mlx5/mlx5_ifc.h, > only log_max_qp_sz is 8 bits wide: > > u8 log_max_qp_sz[0x8]; > > The rd_atomic caps used by validate_rd_atomic() are 6 bits wide: > > u8 log_max_ra_req_dc[0x6]; > u8 log_max_ra_res_dc[0x6]; > u8 log_max_ra_req_qp[0x6]; > u8 log_max_ra_res_qp[0x6]; > > The cap used by set_user_rq_size() is 5 bits wide, so its maximum value > is exactly 31: > > u8 log_max_wq_sz[0x5]; > > The main point still holds, since every one of these fields can reach 31 > and the shift can be undefined. > > Could the wording be changed to something like "a log_max_* FW capability > of up to 8 bits"? > Right, will fix the commit message in V1. Yishai