From: Heiner Kallweit <hkallweit1@gmail.com>
To: Daniel Golle <daniel@makrotopia.org>,
Andrew Lunn <andrew@lunn.ch>,
Russell King <linux@armlinux.org.uk>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Vladimir Oltean <vladimir.oltean@nxp.com>,
Michael Klein <michael@fossekall.de>,
Aleksander Jan Bajkowski <olek2@wp.pl>,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH net-next 2/5] net: phy: realtek: simplify C22 reg access via MDIO_MMD_VEND2
Date: Fri, 9 Jan 2026 08:27:40 +0100 [thread overview]
Message-ID: <65f60d6f-d6f9-4c36-a344-ffc713633dfd@gmail.com> (raw)
In-Reply-To: <938aff8b65ea84eccdf1a2705684298ec33cc5b0.1767926665.git.daniel@makrotopia.org>
On 1/9/2026 4:03 AM, Daniel Golle wrote:
> RealTek 2.5GE PHYs have all standard Clause-22 registers mapped also
> inside MDIO_MMD_VEND2 at offset 0xa400. This is used mainly in case the
> PHY is inside a copper SFP module which uses the RollBall MDIO-over-I2C
> method which *only* supports Clause-45. In order to support such
> modules, the PHY driver has previously been split into a C22-only and
> C45-only instances, creating quite a bit of redundancy and confusion.
>
To complement: RTL812x MAC/PHY chips allow access to MDIO_MMD_VEND2 of the
integrated PHY only. There is no native C22 MDIO access.
> In preparation of reunifying the two driver instances, add support for
> translating MDIO_MMD_VEND2 registers 0xa400 to 0xa438 back to standard
> Clause-22 access in case the PHY is accessed on a Clause-22 bus.
>
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> ---
> drivers/net/phy/realtek/realtek_main.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/net/phy/realtek/realtek_main.c b/drivers/net/phy/realtek/realtek_main.c
> index 7302b25b8908b..886694ff995f6 100644
> --- a/drivers/net/phy/realtek/realtek_main.c
> +++ b/drivers/net/phy/realtek/realtek_main.c
> @@ -143,6 +143,7 @@
>
> #define RTL822X_VND2_TO_PAGE(reg) ((reg) >> 4)
> #define RTL822X_VND2_TO_PAGE_REG(reg) (16 + (((reg) & GENMASK(3, 0)) >> 1))
> +#define RTL822X_VND2_TO_C22_REG(reg) (((reg) - 0xa400) / 2)
> #define RTL822X_VND2_C22_REG(reg) (0xa400 + 2 * (reg))
>
> #define RTL8221B_VND2_INER 0xa4d2
> @@ -1264,6 +1265,11 @@ static int rtl822xb_read_mmd(struct phy_device *phydev, int devnum, u16 reg)
> return mmd_phy_read(phydev->mdio.bus, phydev->mdio.addr,
> phydev->is_c45, devnum, reg);
>
> + /* Simplify access to C22-registers addressed inside MDIO_MMD_VEND2 */
> + if (reg >= RTL822X_VND2_C22_REG(0) &&
> + reg <= RTL822X_VND2_C22_REG(30))
> + return __phy_read(phydev, RTL822X_VND2_TO_C22_REG(reg));
> +
> /* Use paged access for MDIO_MMD_VEND2 over Clause-22 */
> page = RTL822X_VND2_TO_PAGE(reg);
> oldpage = __phy_read(phydev, RTL821x_PAGE_SELECT);
> @@ -1299,6 +1305,11 @@ static int rtl822xb_write_mmd(struct phy_device *phydev, int devnum, u16 reg,
> return mmd_phy_write(phydev->mdio.bus, phydev->mdio.addr,
> phydev->is_c45, devnum, reg, val);
>
> + /* Simplify access to C22-registers addressed inside MDIO_MMD_VEND2 */
> + if (reg >= RTL822X_VND2_C22_REG(0) &&
> + reg <= RTL822X_VND2_C22_REG(30))
> + return __phy_write(phydev, RTL822X_VND2_TO_C22_REG(reg), val);
> +
> /* Use paged access for MDIO_MMD_VEND2 over Clause-22 */
> page = RTL822X_VND2_TO_PAGE(reg);
> oldpage = __phy_read(phydev, RTL821x_PAGE_SELECT);
next prev parent reply other threads:[~2026-01-09 7:27 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-09 3:02 [PATCH net-next 0/5] net: phy: realtek: simplify and reunify C22/C45 drivers Daniel Golle
2026-01-09 3:03 ` [PATCH net-next 1/5] net: phy: realtek: support interrupt also for C22 variants Daniel Golle
2026-01-09 3:03 ` [PATCH net-next 2/5] net: phy: realtek: simplify C22 reg access via MDIO_MMD_VEND2 Daniel Golle
2026-01-09 7:27 ` Heiner Kallweit [this message]
2026-01-09 21:32 ` Russell King (Oracle)
2026-01-09 22:21 ` Daniel Golle
2026-01-09 3:03 ` [PATCH net-next 3/5] net: phy: realtek: reunify C22 and C45 drivers Daniel Golle
2026-01-09 13:18 ` Andrew Lunn
2026-01-09 13:25 ` Daniel Golle
2026-01-10 14:28 ` Heiner Kallweit
2026-01-09 3:03 ` [PATCH net-next 4/5] net: phy: realtek: demystify PHYSR register location Daniel Golle
2026-01-09 7:32 ` Heiner Kallweit
2026-01-09 12:26 ` Daniel Golle
2026-01-09 17:31 ` Daniel Golle
2026-01-09 20:19 ` Daniel Golle
2026-01-09 3:03 ` [PATCH net-next 5/5] net: phy: realtek: simplify bogus paged operations Daniel Golle
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