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Miller" , Eric Dumazet , Vlad Buslov , Simon Horman , Khalid Manaa , =?UTF-8?B?VG9rZSBIw7hpbGFuZC1Kw7hyZ2Vuc2Vu?= , Victor Nogueira , "Tammela, Pedro" , "Daly, Dan" , Andy Fingerhut , "Sommers, Chris" , Matty Kadosh , bpf , "lwn@lwn.net" Message-ID: <66563bc85f5d0_2f7f2087@john.notmuch> In-Reply-To: References: <20240410140141.495384-1-jhs@mojatatu.com> <41736ea4e81666e911fee5b880d9430ffffa9a58.camel@redhat.com> <87cf4830e2e46c1882998162526e108fb424a0f7.camel@redhat.com> <82ee1013ca0164053e9fb1259eaf676343c430e8.camel@redhat.com> <20240522151933.6f422e63@kernel.org> Subject: Re: On the NACKs on P4TC patches Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Jain, Vipin wrote: > [AMD Official Use Only - AMD Internal Distribution Only] > = > My apologies, earlier email used html and was blocked by the list... > My response at the bottom as "VJ>" > = > ________________________________________ > From: Jain, Vipin > Sent: Friday, May 24, 2024 2:28 PM > To: Singhai, Anjali ; Hadi Salim, Jamal ; Jakub Kicinski > Cc: Paolo Abeni ; Alexei Starovoitov ; Network Development ; Chatterjee= , Deb ; Limaye, Namrata ; tom Herbert ; Marcelo Ricardo Leitner ; Shirshyad, Mahesh ; Osinski, Tomasz ; Jiri Pirko ; Cong Wang ; David S. Miller ; Eric Dumazet= ; Vlad Buslov ; Simon Horman ; Khalid Manaa ; Toke H=C3=B8iland-J=C3= =B8rgensen ; Victor Nogueira ; Tamm= ela, Pedro ; Daly, Dan ; Andy= Fingerhut ; Sommers, Chris ; Matty Kadosh ; bpf ; l= wn@lwn.net > Subject: Re: On the NACKs on P4TC patches > = > [AMD Official Use Only - AMD Internal Distribution Only] > = > = > I can ascertain (from AMD) that we have stated interest in, and are in = full support of P4TC. > = > Happy to elaborate more if needed. > = > Thank you, > Vipin Jain > Sr Fellow Engineer, AMD > ________________________________________ > From: Singhai, Anjali > Sent: Wednesday, May 22, 2024 5:30 PM > To: Hadi Salim, Jamal ; Jakub Kicinski > Cc: Paolo Abeni ; Alexei Starovoitov ; Network Development ; Chatterjee= , Deb ; Limaye, Namrata ; tom Herbert ; Marcelo Ricardo Leitner ; Shirshyad, Mahesh ; Osinski, Tomasz ; Jiri Pirko ; Cong Wang ; David S. Miller ; Eric Dumazet= ; Vlad Buslov ; Simon Horman ; Khalid Manaa ; Toke H=C3=B8iland-J=C3= =B8rgensen ; Victor Nogueira ; Tamm= ela, Pedro ; Jain, Vipin ; Da= ly, Dan ; Andy Fingerhut ; = Sommers, Chris ; Matty Kadosh ; bpf ; lwn@lwn.net > Subject: RE: On the NACKs on P4TC patches > = > Caution: This message originated from an External Source. Use proper ca= ution when opening attachments, clicking links, or responding. > = > = > On Wed, May 22, 2024 at 6:19=E2=80=AFPM Jakub Kicinski wrote: > = > >> AFAICT there's some but not very strong support for P4TC, > = > On Wed, May 22, 2024 at 4:04=E2=80=AFPM Jamal Hadi Salim wrote: > >I dont agree. Paolo asked this question and afaik Intel, AMD (both bui= ld P4-native NICs) and the folks interested in the MS DASH project >respo= nded saying they are in support. Look at who is being Cced. A lot of thes= e folks who attend biweekly discussion calls on P4TC. >Sample: > >https://lore.kernel.org/netdev/IA0PR17MB7070B51A955FB8595FFBA5FB965E2@= IA0PR17MB7070.namprd17.prod.outlook.com/ > = > FWIW, Intel is in full support of P4TC as we have stated several times = in the past. > VJ> I can ascertain (from AMD) that we have stated interest in, and are= in full support of P4TC. Happy to elaborate more if needed. > VJ> Thanks, Vipin Anjali and Vipin is your support for HW support of P4 or a Linux SW imple= mentation of P4. If its for HW support what drivers would we want to support? Can y= ou describe how to program these devices? At the moment there hasn't been any movement on Linux hardware P4 support= side as far as I can tell. Yes there are some SDKs and build kits floating aro= und for FPGAs. For example maybe start with what drivers in kernel tree run the D= PUs that have this support? I think this would be a productive direction to go if = we in fact have hardware support in the works. If you want a SW implementation in Linux my opinion is still pushing a DS= L into the kernel datapath via qdisc/tc is the wrong direction. Mapping P4 onto hardware blocks is fundamentally different architecture from mapping= P4 onto general purpose CPU and registers. My opinion -- to handle this y= ou need a per architecture backend/JIT to compile the P4 to native instructi= ons. This will give you the most flexibility to define new constructs, best performance, and lowest overhead runtime. We have a P4 BPF backend alread= y and JITs for most architectures I don't see the need for P4TC in this context. If the end goal is a hardware offload control plane I'm skeptical we even need something specific just for SW datapath. I would propose a devlink or new infra to program the device directly vs overhead and complexity of abstracting through 'tc'. If you want to emulate your device use BPF or user space datapath. .John=