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Wed, 8 Jan 2025 05:19:52 +0000 Date: Tue, 7 Jan 2025 21:19:50 -0800 From: Dan Williams To: , , , , , , , , , , CC: Alejandro Lucero Subject: Re: [PATCH v8 05/27] cxl: move pci generic code Message-ID: <677e0af67788e_2aff429448@dwillia2-xfh.jf.intel.com.notmuch> References: <20241216161042.42108-1-alejandro.lucero-palau@amd.com> <20241216161042.42108-6-alejandro.lucero-palau@amd.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20241216161042.42108-6-alejandro.lucero-palau@amd.com> X-ClientProxiedBy: MW4P223CA0008.NAMP223.PROD.OUTLOOK.COM (2603:10b6:303:80::13) To PH8PR11MB8107.namprd11.prod.outlook.com (2603:10b6:510:256::6) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8107:EE_|DS7PR11MB5992:EE_ X-MS-Office365-Filtering-Correlation-Id: 195713d3-e230-4927-3475-08dd2fa414e4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|7416014|376014|1800799024|921020; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?ml3WXLoxc+KXKcN1sxgROPjAXJ5UmMMPV/URfqenBDq8RCrfPGfKsqe7b/Xn?= =?us-ascii?Q?+oqpStdLnYygy32WffUTAJHCaxKMjdSOSCqn/HvvxE9YV9+4wprPKUfZNLue?= =?us-ascii?Q?TWqv/elBd4fmu6XoBt/nX8vfbsYMywoUFxit9B1XHCY+BKA2rlLE5i2IkA3k?= =?us-ascii?Q?Y3QxvT9O28XnU9JikgPF21J2rqXJdrEuv3kfZbsCYt+4qR/NCta/mf2v+Hbl?= =?us-ascii?Q?EV5e91Cafuip25GNrsloao0Hi+G4wn6DGUfkYQtrDjkeY1J+RCmnnUQPXymD?= =?us-ascii?Q?WtJ+9yftzI0hBK5a5080KTUdA/zlD4Aqhrn74Yf4sGgHt3eGlyiEwFNrlkv3?= =?us-ascii?Q?CyQRohxNgio1DvmLOa0Qaxkjhkn3WUxICAdgnS2O57vJxQ7qYg5dSzZMY3jC?= =?us-ascii?Q?hCIecCIUzce/Mqd0gxPhX7OGZtTcJEvYismcxeWWB1vl/OFP4+hnDW/uTG36?= =?us-ascii?Q?gaeakFuC0Qw1Wqo7JpcBaWHKqSWvulUU8Dz3bUaIEWa9ukEWrC2PRBo6AbGG?= =?us-ascii?Q?abbtasu/Cj5TctLqoWK/QNxR4jiDFeleNLJ1gxgTPkm4gcqj0BljjdmBjdAk?= =?us-ascii?Q?B5dkZiqQU1YM47LA5iD2xzqQvVmEC+5vRVVZL6AywS2g3NvrUhXpUPWaNSP5?= =?us-ascii?Q?tQudlRP/KiHuU/GPYD0uwS+GhiGWRS/DjgDOjQOjMdJqjlKjMHZxmqwfZ87a?= =?us-ascii?Q?ON/Kx5aBg19Q4WLoC4zG7TmljbP9oyouvVLHh3rcO5CA4u6OX06SaiY8/oq1?= =?us-ascii?Q?u02ukjOZL1v+NYzSPr1TRa5ObvnRjml0LPCga5ldrTD+fWthKcphWXQgfqrP?= =?us-ascii?Q?fb5hO16d89NqSTS8OrVe+8pukvvFGFmU/rbjKWN3Br8jFjGOxdhR9F2WKTX7?= =?us-ascii?Q?Fzo0DFM02Yg90D5/F/5vSXJZ86nVx54tD/dRdiwElA4CDj5+aWI1zfZd9n4q?= =?us-ascii?Q?Ogzc2/8zv6zoqdYSOMdg+lhwy35MZokj3bXzGmGLXR4NQUoAva0336ulYoAB?= =?us-ascii?Q?YrrmHd5aYSVgsOqmfkKPGcQv4GUtuWvrfN7zn/oF2QV8sL2k4dLDcHZVttMP?= =?us-ascii?Q?4VSVGLNsHhWcYRdQVCrpuqUtVkR740KOFB5ndD2r866goJkiQ2oukS2d2g3R?= =?us-ascii?Q?wj2XxpDSeL1R9yOyUTlxdLk+QA7YavUtV+kGOfSiolhfC9hXbLA97MN/QtrB?= =?us-ascii?Q?0SCFgumX+w4+uObtO9oAzRjnNu2R8toON4pfK5HXkl27h9UCAVTFjvDr1H/u?= =?us-ascii?Q?bN22ZCJqNTt8in2JUY6h4dCYAyOu3qiZ1s6PqIEmJ3MxVusCGTkQGQEhfgPZ?= =?us-ascii?Q?rKVB75JY0Kbuj30J7jIJS9nW69dFUPPeerTLlqe2wb2qQBZ1FYN3Vl/kVRhy?= =?us-ascii?Q?6e9Xk+LG7ilxP+I3u5GFaen5ZKcGZgCs6GlL//n1hoQC4BRA3ogno/VkIiNg?= =?us-ascii?Q?7UrXDyOSrKGTOnNcA8pvQcvxrKW5LRMTqZ2UZFysjBYQfTvEEWnuJfndEDmr?= =?us-ascii?Q?/l/zt1k4HrxCr9rr7l6Hq69Zh3pnO4lfZZaNb0urZjXPk3zC+M19y7t6xpWn?= =?us-ascii?Q?8aPYoJx+17GKeW9+d2OgUDyFVvxMUsw2BiEEiH22DI4WQZU6LBYLUSS9I2NC?= =?us-ascii?Q?CA=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 195713d3-e230-4927-3475-08dd2fa414e4 X-MS-Exchange-CrossTenant-AuthSource: PH8PR11MB8107.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jan 2025 05:19:52.9291 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: WnYIR0n9MwOnLxzVMOoDKyU/I+zX+ZWjCVzU1mKZw8apWCF68KfpHKd0Sea+OUJfyF9qsujSSETdqkInOj5P1uG4x0Y/HcPTpIB9bOvd6Nc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR11MB5992 X-OriginatorOrg: intel.com alejandro.lucero-palau@ wrote: > From: Alejandro Lucero > > Inside cxl/core/pci.c there are helpers for CXL PCIe initialization > meanwhile cxl/pci.c implements the functionality for a Type3 device > initialization. > > Move helper functions from cxl/pci.c to cxl/core/pci.c in order to be > exported and shared with CXL Type2 device initialization. > > Signed-off-by: Alejandro Lucero > Reviewed-by: Dave Jiang > Reviewed-by: Ben Cheatham > Reviewed-by: Fan Ni This is the patch that causes the cxl-test build error... > --- > drivers/cxl/core/pci.c | 62 ++++++++++++++++++++++++++++++++++++ > drivers/cxl/cxlpci.h | 3 ++ > drivers/cxl/pci.c | 71 ------------------------------------------ > 3 files changed, 65 insertions(+), 71 deletions(-) > > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index bc098b2ce55d..3cca3ae438cd 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -1034,6 +1034,68 @@ bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port) > } > EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_reset_detected, "CXL"); > > +/* > + * Assume that any RCIEP that emits the CXL memory expander class code > + * is an RCD > + */ > +bool is_cxl_restricted(struct pci_dev *pdev) > +{ > + return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; > +} > +EXPORT_SYMBOL_NS_GPL(is_cxl_restricted, "CXL"); > + > +static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, > + struct cxl_register_map *map) > +{ > + struct cxl_port *port; > + struct cxl_dport *dport; > + resource_size_t component_reg_phys; > + > + *map = (struct cxl_register_map) { > + .host = &pdev->dev, > + .resource = CXL_RESOURCE_NONE, > + }; > + > + port = cxl_pci_find_port(pdev, &dport); > + if (!port) > + return -EPROBE_DEFER; > + > + component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport); ...and it is in part due to failing to notice that cxl_rcd_component_reg_phys() no longer needs to be exported once cxl_pci_setup_regs() move to the core. Please make sure there are not other occurrences of EXPORT_SYMBOL() cleanups that can be done in this series. Again, as I do not want to inflict cxl-test and --wrap= debugging on folks, here is an incremental fixup/cleanup below. Note how I fixed up the is_cxl_restricted() comment to make it relevant for the accelerator case. Please don't leave stale comments around when moving code. Also note renaming the header guard to something more appropriate for include/cxl/pci.h. That should be folded back to patch1. -- 8< -- diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 800466f96a68..3b33470b8cbc 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -107,6 +107,8 @@ enum cxl_poison_trace_type { CXL_POISON_TRACE_CLEAR, }; +resource_size_t cxl_rcd_component_reg_phys(struct device *dev, + struct cxl_dport *dport); long cxl_pci_get_latency(struct pci_dev *pdev); int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c); int cxl_update_hmat_access_coordinates(int nid, struct cxl_region *cxlr, diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index aaea29bff0f1..afa3bd872dc0 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -1034,16 +1034,6 @@ bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_reset_detected, "CXL"); -/* - * Assume that any RCIEP that emits the CXL memory expander class code - * is an RCD - */ -bool is_cxl_restricted(struct pci_dev *pdev) -{ - return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; -} -EXPORT_SYMBOL_NS_GPL(is_cxl_restricted, "CXL"); - static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, struct cxl_register_map *map, struct cxl_dport *dport) diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 6432a784f08b..0a218385c480 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -633,4 +633,3 @@ resource_size_t cxl_rcd_component_reg_phys(struct device *dev, return CXL_RESOURCE_NONE; return __rcrb_to_component(dev, &dport->rcrb, CXL_RCRB_UPSTREAM); } -EXPORT_SYMBOL_NS_GPL(cxl_rcd_component_reg_phys, "CXL"); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 22e787748d79..8f241d87127a 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -311,8 +311,6 @@ int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map); int cxl_setup_regs(struct cxl_register_map *map, unsigned long *caps); struct cxl_dport; -resource_size_t cxl_rcd_component_reg_phys(struct device *dev, - struct cxl_dport *dport); int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport); #define CXL_RESOURCE_NONE ((resource_size_t) -1) diff --git a/include/cxl/pci.h b/include/cxl/pci.h index ad63560caa2c..efed17bc9274 100644 --- a/include/cxl/pci.h +++ b/include/cxl/pci.h @@ -1,8 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ -#ifndef __CXL_ACCEL_PCI_H -#define __CXL_ACCEL_PCI_H +#ifndef __LINUX_CXL_PCI_H__ +#define __LINUX_CXL_PCI_H__ + +#include + +/* + * Assume that the caller has already validated that @pdev has CXL + * capabilities, any RCIEp with CXL capabilities is treated as a + * Restricted CXL Device (RCD) and finds upstream port and endpoint + * registers in a Root Complex Register Block (RCRB) + */ +static inline bool is_cxl_restricted(struct pci_dev *pdev) +{ + return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; +} /* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */ #define CXL_DVSEC_PCIE_DEVICE 0 diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index b1256fee3567..e20d0e767574 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -12,7 +12,6 @@ ldflags-y += --wrap=cxl_await_media_ready ldflags-y += --wrap=cxl_hdm_decode_init ldflags-y += --wrap=cxl_dvsec_rr_decode ldflags-y += --wrap=devm_cxl_add_rch_dport -ldflags-y += --wrap=cxl_rcd_component_reg_phys ldflags-y += --wrap=cxl_endpoint_parse_cdat ldflags-y += --wrap=cxl_dport_init_ras_reporting diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c index 450c7566c33f..af7a5ae09ef8 100644 --- a/tools/testing/cxl/test/mock.c +++ b/tools/testing/cxl/test/mock.c @@ -268,23 +268,6 @@ struct cxl_dport *__wrap_devm_cxl_add_rch_dport(struct cxl_port *port, } EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_add_rch_dport, "CXL"); -resource_size_t __wrap_cxl_rcd_component_reg_phys(struct device *dev, - struct cxl_dport *dport) -{ - int index; - resource_size_t component_reg_phys; - struct cxl_mock_ops *ops = get_cxl_mock_ops(&index); - - if (ops && ops->is_mock_port(dev)) - component_reg_phys = CXL_RESOURCE_NONE; - else - component_reg_phys = cxl_rcd_component_reg_phys(dev, dport); - put_cxl_mock_ops(index); - - return component_reg_phys; -} -EXPORT_SYMBOL_NS_GPL(__wrap_cxl_rcd_component_reg_phys, "CXL"); - void __wrap_cxl_endpoint_parse_cdat(struct cxl_port *port) { int index;