[PATCH v9 06/27] cxl: add function for type2 cxl regs setup

alejandro.lucero-palau
2024-12-30T21:45:11Z

From: Alejandro Lucero <alucerop@amd.com>

Create a new function for a type2 device initialising
cxl_dev_state struct regarding cxl regs setup and mapping.

Signed-off-by: Alejandro Lucero <alucerop@amd.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
---
drivers/cxl/core/pci.c | 51 ++++++++++++++++++++++++++++++++++++++++++
include/cxl/cxl.h | 2 ++
2 files changed, 53 insertions(+)

diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 5821d582c520..493ab33fe771 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -1107,6 +1107,57 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
}
EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, "CXL");

+static int cxl_pci_setup_memdev_regs(struct pci_dev *pdev,
+ struct cxl_dev_state *cxlds)
+{
+ struct cxl_register_map map;
+ int rc;
+
+ rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map,
+ cxlds->capabilities);
+ /*
+ * This call can return -ENODEV if regs not found. This is not an error
+ * for Type2 since these regs are not mandatory. If they do exist then
+ * mapping them should not fail. If they should exist, it is with driver
+ * calling cxl_pci_check_caps where the problem should be found.
+ */
+ if (rc == -ENODEV)
+ return 0;
+
+ if (rc)
+ return rc;
+
+ return cxl_map_device_regs(&map, &cxlds->regs.device_regs);
+}
+
+int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds)
+{
+ int rc;
+
+ rc = cxl_pci_setup_memdev_regs(pdev, cxlds);
+ if (rc)
+ return rc;
+
+ rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT,
+ &cxlds->reg_map, cxlds->capabilities);
+ if (rc) {
+ dev_warn(&pdev->dev, "No component registers (%d)\n", rc);
+ return rc;
+ }
+
+ if (!test_bit(CXL_CM_CAP_CAP_ID_RAS, cxlds->capabilities))
+ return rc;
+
+ rc = cxl_map_component_regs(&cxlds->reg_map,
+ &cxlds->regs.component,
+ BIT(CXL_CM_CAP_CAP_ID_RAS));
+ if (rc)
+ dev_dbg(&pdev->dev, "Failed to map RAS capability.\n");
+
+ return rc;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_pci_accel_setup_regs, "CXL");
+
int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c)
{
int speed, bw;
diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
index 464e5fb006ba..c1bb0359476c 100644
--- a/include/cxl/cxl.h
+++ b/include/cxl/cxl.h
@@ -43,4 +43,6 @@ int cxl_set_resource(struct cxl_dev_state *cxlds, struct resource res,
bool cxl_pci_check_caps(struct cxl_dev_state *cxlds,
unsigned long *expected_caps,
unsigned long *current_caps);
+struct pci_dev;
+int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds);
#endif
--
2.17.1