[PATCH v9 07/27] sfc: use cxl api for regs setup and checking

alejandro.lucero-palau
2024-12-30T21:45:13Z

From: Alejandro Lucero <alucerop@amd.com>

Use cxl code for registers discovery and mapping.

Validate capabilities found based on those registers against expected
capabilities.

Signed-off-by: Alejandro Lucero <alucerop@amd.com>
Reviewed-by: Martin Habets <habetsm.xilinx@gmail.com>
Reviewed-by: Zhi Wang <zhi@nvidia.com>
Acked-by: Edward Cree <ecree.xilinx@gmail.com>
---
drivers/net/ethernet/sfc/efx_cxl.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)

diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c
index 12c9d50cbb26..29368d010adc 100644
--- a/drivers/net/ethernet/sfc/efx_cxl.c
+++ b/drivers/net/ethernet/sfc/efx_cxl.c
@@ -22,6 +22,8 @@ int efx_cxl_init(struct efx_probe_data *probe_data)
{
struct efx_nic *efx = &probe_data->efx;
struct pci_dev *pci_dev = efx->pci_dev;
+ DECLARE_BITMAP(expected, CXL_MAX_CAPS);
+ DECLARE_BITMAP(found, CXL_MAX_CAPS);
struct efx_cxl *cxl;
struct resource res;
u16 dvsec;
@@ -64,6 +66,25 @@ int efx_cxl_init(struct efx_probe_data *probe_data)
goto err_resource_set;
}

+ rc = cxl_pci_accel_setup_regs(pci_dev, cxl->cxlds);
+ if (rc) {
+ pci_err(pci_dev, "CXL accel setup regs failed");
+ goto err_resource_set;
+ }
+
+ bitmap_clear(expected, 0, CXL_MAX_CAPS);
+ set_bit(CXL_DEV_CAP_HDM, expected);
+ set_bit(CXL_DEV_CAP_HDM, expected);
+ set_bit(CXL_DEV_CAP_RAS, expected);
+
+ if (!cxl_pci_check_caps(cxl->cxlds, expected, found)) {
+ pci_err(pci_dev,
+ "CXL device capabilities found(%pb) not as expected(%pb)",
+ found, expected);
+ rc = -EIO;
+ goto err_resource_set;
+ }
+
probe_data->cxl = cxl;

return 0;
--
2.17.1