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Tue, 21 Jan 2025 22:51:38 +0000 Date: Tue, 21 Jan 2025 14:51:36 -0800 From: Dan Williams To: Alejandro Lucero Palau , Dan Williams , , , , , , , , , Subject: Re: [PATCH v9 06/27] cxl: add function for type2 cxl regs setup Message-ID: <679024f84230f_20fa29478@dwillia2-xfh.jf.intel.com.notmuch> References: <20241230214445.27602-1-alejandro.lucero-palau@amd.com> <20241230214445.27602-7-alejandro.lucero-palau@amd.com> <678b092428a86_20fa29462@dwillia2-xfh.jf.intel.com.notmuch> <0063f9c6-9263-bc4a-c159-41f9df236a7c@amd.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <0063f9c6-9263-bc4a-c159-41f9df236a7c@amd.com> X-ClientProxiedBy: MW4P221CA0020.NAMP221.PROD.OUTLOOK.COM (2603:10b6:303:8b::25) To PH8PR11MB8107.namprd11.prod.outlook.com (2603:10b6:510:256::6) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8107:EE_|PH0PR11MB7521:EE_ X-MS-Office365-Filtering-Correlation-Id: 8269b489-5a60-4148-85bf-08dd3a6e2a51 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|376014|7053199007|921020; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?fWGnSkAkZPG/Be0i7qg7pGROiRJVW9QX5ttSb8HD37lLoSsEp7rSYuMsoSkv?= =?us-ascii?Q?50oxyj3McKpEF2xOMmx0mfhvKMfeJzBYwv4xbpJyEBEVfkl8En7pzZssWLgS?= =?us-ascii?Q?Nw35LUMOaMq5iSbnkl2eOwEytfM5iPQqC/siVuzaZKL9NJYvgoPoHwhCA6qi?= =?us-ascii?Q?8ZRPwlUYNoYG1ubcikZRYKusCxDM3ISnUb4Ihi7x4x2rcea7pRu5A7BPcF5y?= =?us-ascii?Q?TsjX2+NhsxLZiaIJGTazrBUl9DyA8+QvbgU3cld17WSRzFnHZX/XDbhVPZBw?= =?us-ascii?Q?3IsxdImHOcxlIJk6Cd3wzk+JCwGMtu/d7BupBlEVrC1c9Dkeh48n8Gr5o+LX?= =?us-ascii?Q?WhH2EW/eEcW4p9jzEdgxgxMgH98AEfEu9mjKlg9puBYCi7SgYtpQ+8Ahf41L?= =?us-ascii?Q?rNEgJghvwq5j+EFxrhoszUoy4S6MJo+qdBFmWWIgYexm01byggS1ZcYGEnDb?= =?us-ascii?Q?coJXwONGTDZfI5qe2NAP3IK+qJfXlNi8prcZEg8kzd8vIhgtaQSqytvL2uPp?= =?us-ascii?Q?jW+ACgmlwzjy1bnxgQcvpmhxZxbXVHbJ9L/0oY2etOhx533p36vewGGN1m51?= =?us-ascii?Q?yMlbYkwMWvGkNQSJbpX3x0VecWWQ5EzD6RCh5v6zOjbpUN1VohTPzy+qVuKr?= =?us-ascii?Q?619ZiDZFZwR6xcykQ+9gyjjd/bpQ45c4Os4tGw3qH3YHu5KH6AoDhCTdtr0O?= =?us-ascii?Q?HbWTj90qsjg89Pu8ssBOfsn8mJBIAQsOASeizBjoabk0az3Ffei6+xLL9Ex2?= =?us-ascii?Q?encVxNrRjZS7WvgK6sBkchZ5TlwHvTxTd+GAwmCDQ1qCTf5+ilvd/6rzbKDk?= =?us-ascii?Q?MxgG+CxUD71z24v6i52VIMzELfzu1rlbrzxjyA/IcDDKAjfS/lrMqHBVrPXU?= =?us-ascii?Q?DQQqRAv0PAw3m1ohF2F4+7PrD22BaQVcVj1qVdd9ZnajLBgN22m0D0jrglV3?= =?us-ascii?Q?dPuCOdR5MFL/OnGrEREV7ojKuo4X0KhcWNeDtEv8U+0pAuLcNXA33oYsylKZ?= =?us-ascii?Q?7LDH0ddGvZLCGC7TAb99DMelaMMSVr3SlTwji8/Kt8MEkbVUburiwp5byURr?= =?us-ascii?Q?KPp6REDNDWCdyNyG6S+56gOx/ClIfkKDsFZ1BsxIaWg2Q4i+lAyMU2HofkFH?= =?us-ascii?Q?fNCQtxLppk6xqaiKuxlmcYiNZaxJuv6zHBk7BXOn5SKMbh7krPXMy8ZxSKJf?= =?us-ascii?Q?WpJm2N6WD7WHOStYXBMZ5rVnADC3M50m72Tzqm9Y/gzOAe/cDHSdMgzmySbC?= =?us-ascii?Q?ALK9tSw5/ybXHIYezINzxbtZOqh4Q81LeNT8yp+setpJIzVAj706PMmYF8N9?= =?us-ascii?Q?Qh3aPAZS+Rk9t+RSQz5OY1ChBx1RZ9o/OFWmcwLypnuU0JZqho8mk89AVF4b?= =?us-ascii?Q?SjMfeLW8gemiPpoIB7wwZLNvq/w1I2J0ywZTdPWDjN5IXft2mwrvL/wvZtLA?= =?us-ascii?Q?E1GsegKAKfAWOx+fpaNkrcGeAhOMS7HxM3eV/JXuE5B7iHJ5n6fmFhOHXmJS?= =?us-ascii?Q?AmDc0xBLMpr5j6C4lglHiyCfaHrbqUtGOaEKnhK41ghwTW0HYZpzhpfxf+zf?= =?us-ascii?Q?bK+onnyZYWJ5T7TRliuY7kPNH/15EHjpiUMRTMifCYsINSXuR4fjhgLjP2b+?= =?us-ascii?Q?KQ=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 8269b489-5a60-4148-85bf-08dd3a6e2a51 X-MS-Exchange-CrossTenant-AuthSource: PH8PR11MB8107.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jan 2025 22:51:38.8478 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: TjOmDRz3TEvHOtBrCFhP26uZ0uHpX/9TinmZIcC7fmCspzopz3RkzaksMxfZufXOp+KrPbMPX/jL6BZBAVlnmZUa/V4qzJFAEquDczvOUGE= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR11MB7521 X-OriginatorOrg: intel.com Alejandro Lucero Palau wrote: > > On 1/18/25 01:51, Dan Williams wrote: > > alejandro.lucero-palau@ wrote: > >> From: Alejandro Lucero > >> > >> Create a new function for a type2 device initialising > >> cxl_dev_state struct regarding cxl regs setup and mapping. > >> > >> Signed-off-by: Alejandro Lucero > >> Reviewed-by: Dave Jiang > >> Reviewed-by: Fan Ni > >> --- > >> drivers/cxl/core/pci.c | 51 ++++++++++++++++++++++++++++++++++++++++++ > >> include/cxl/cxl.h | 2 ++ > >> 2 files changed, 53 insertions(+) > >> > >> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > >> index 5821d582c520..493ab33fe771 100644 > >> --- a/drivers/cxl/core/pci.c > >> +++ b/drivers/cxl/core/pci.c > >> @@ -1107,6 +1107,57 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, > >> } > >> EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, "CXL"); > >> > >> +static int cxl_pci_setup_memdev_regs(struct pci_dev *pdev, > >> + struct cxl_dev_state *cxlds) > >> +{ > >> + struct cxl_register_map map; > >> + int rc; > >> + > >> + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, > >> + cxlds->capabilities); > >> + /* > >> + * This call can return -ENODEV if regs not found. This is not an error > >> + * for Type2 since these regs are not mandatory. If they do exist then > >> + * mapping them should not fail. If they should exist, it is with driver > >> + * calling cxl_pci_check_caps where the problem should be found. > >> + */ > > There is no common definition of type-2 so the core should not try to > > assume it knows, or be told what is mandatory. Just export the raw > > helpers and leave it to the caller to make these decisions. > > > The code does not know, but it knows it does not know, therefore handles > this new situation not needed before Type2 support in the generic code > for the pci driver and Type3. > > This is added to the API for accel drivers following the design > restrictions I have commented earlier in another patch. Your suggestion > seems to go against that decision what was implicitly taken after the > first versions and which had no complains until now. Apologies for that, I had not looked at the implications of that general decision until now, but the result is going in the wrong direction from what it is doing to the core. > >> + return 0; > >> + > >> + if (rc) > >> + return rc; > >> + > >> + return cxl_map_device_regs(&map, &cxlds->regs.device_regs); > >> +} > >> + > >> +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) > >> +{ > >> + int rc; > >> + > >> + rc = cxl_pci_setup_memdev_regs(pdev, cxlds); > >> + if (rc) > >> + return rc; > >> + > >> + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, > >> + &cxlds->reg_map, cxlds->capabilities); > >> + if (rc) { > >> + dev_warn(&pdev->dev, "No component registers (%d)\n", rc); > >> + return rc; > >> + } > >> + > >> + if (!test_bit(CXL_CM_CAP_CAP_ID_RAS, cxlds->capabilities)) > >> + return rc; This is injecting logic in a bitmap and a new CXL core exported ABI just to avoid the driver optionally skipping RAS register enumeration. The core should not care how and whether endpoint drivers (accel or cxl_pci) consume register blocks, just arrange for their enumeration and let the leaf driver logic take it from there.