From: Ira Weiny <ira.weiny@intel.com>
To: <alucerop@amd.com>, <linux-cxl@vger.kernel.org>,
<netdev@vger.kernel.org>, <dan.j.williams@intel.com>,
<edward.cree@amd.com>, <davem@davemloft.net>, <kuba@kernel.org>,
<pabeni@redhat.com>, <edumazet@google.com>,
<dave.jiang@intel.com>
Cc: Alejandro Lucero <alucerop@amd.com>
Subject: Re: [PATCH v10 09/26] cxl: support device identification without mailbox
Date: Wed, 5 Feb 2025 15:45:36 -0600 [thread overview]
Message-ID: <67a3dc0071693_2ee275294fc@iweiny-mobl.notmuch> (raw)
In-Reply-To: <20250205151950.25268-10-alucerop@amd.com>
alucerop@ wrote:
> From: Alejandro Lucero <alucerop@amd.com>
>
> Type3 relies on mailbox CXL_MBOX_OP_IDENTIFY command for initializing
> memdev state params.
>
> Allow a Type2 driver to initialize same params using an info struct and
> assume partition alignment not required by now.
>
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
This is exactly the type of thing I was hoping to avoid by removing these
members from the mds. There is no reason you should have to fake these
values within an mds just to create partitions in the device state.
Still wrapping my head around the entire series though...
Ira
> ---
> drivers/cxl/core/memdev.c | 12 ++++++++++++
> include/cxl/cxl.h | 11 +++++++++++
> 2 files changed, 23 insertions(+)
>
> diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
> index 456d505f1bc8..7113a51b3a93 100644
> --- a/drivers/cxl/core/memdev.c
> +++ b/drivers/cxl/core/memdev.c
> @@ -655,6 +655,18 @@ struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev, u64 serial,
> }
> EXPORT_SYMBOL_NS_GPL(cxl_memdev_state_create, "CXL");
>
> +void cxl_dev_state_setup(struct cxl_memdev_state *mds, struct mds_info *info)
> +{
> + if (!mds->cxlds.media_ready)
> + return;
> +
> + mds->total_bytes = info->total_bytes;
> + mds->volatile_only_bytes = info->volatile_only_bytes;
> + mds->persistent_only_bytes = info->persistent_only_bytes;
> + mds->partition_align_bytes = 0;
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_dev_state_setup, "CXL");
> +
> static struct cxl_memdev *cxl_memdev_alloc(struct cxl_dev_state *cxlds,
> const struct file_operations *fops)
> {
> diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
> index 955e58103df6..1b2224ee1d5b 100644
> --- a/include/cxl/cxl.h
> +++ b/include/cxl/cxl.h
> @@ -39,6 +39,16 @@ enum cxl_devtype {
> CXL_DEVTYPE_CLASSMEM,
> };
>
> +/*
> + * struct for an accel driver giving partition data when Type2 device without a
> + * mailbox.
> + */
> +struct mds_info {
> + u64 total_bytes;
> + u64 volatile_only_bytes;
> + u64 persistent_only_bytes;
> +};
> +
> struct device;
> struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev, u64 serial,
> u16 dvsec, enum cxl_devtype type);
> @@ -48,4 +58,5 @@ int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_memdev_state *cxlm
> unsigned long *caps);
> int cxl_await_media_ready(struct cxl_memdev_state *mds);
> void cxl_set_media_ready(struct cxl_memdev_state *mds);
> +void cxl_dev_state_setup(struct cxl_memdev_state *mds, struct mds_info *info);
> #endif
> --
> 2.17.1
>
>
next prev parent reply other threads:[~2025-02-05 21:46 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-05 15:19 [PATCH v10 00/26] cxl: add type2 device basic support alucerop
2025-02-05 15:19 ` [PATCH v10 01/26] cxl: make memdev creation type agnostic alucerop
2025-02-06 19:37 ` Dan Williams
2025-02-17 12:32 ` Alejandro Lucero Palau
2025-02-19 2:29 ` Dan Williams
2025-02-20 18:17 ` Alejandro Lucero Palau
2025-02-17 13:05 ` Alejandro Lucero Palau
2025-02-13 3:57 ` Alison Schofield
2025-02-17 12:49 ` Alejandro Lucero Palau
2025-02-17 13:06 ` Alejandro Lucero Palau
2025-02-14 17:02 ` Jonathan Cameron
2025-02-17 13:08 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 02/26] sfc: add basic cxl initialization alucerop
2025-02-06 1:37 ` Edward Cree
2025-02-07 12:48 ` Simon Horman
2025-02-17 13:10 ` Alejandro Lucero Palau
2025-02-07 13:03 ` Simon Horman
2025-02-17 13:11 ` Alejandro Lucero Palau
2025-02-18 13:32 ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 03/26] cxl: move pci generic code alucerop
2025-02-05 21:33 ` Ira Weiny
2025-02-06 17:49 ` Alejandro Lucero Palau
2025-02-14 17:11 ` Jonathan Cameron
2025-02-17 13:13 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 04/26] cxl: move register/capability check to driver alucerop
2025-02-07 12:52 ` Simon Horman
2025-02-17 13:17 ` Alejandro Lucero Palau
2025-02-14 17:21 ` Jonathan Cameron
2025-02-17 13:18 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 05/26] cxl: add function for type2 cxl regs setup alucerop
2025-02-05 21:35 ` Ira Weiny
2025-02-06 17:50 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 06/26] sfc: use cxl api for regs setup and checking alucerop
2025-02-05 21:31 ` Ira Weiny
2025-02-06 17:47 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 07/26] cxl: add support for setting media ready by an accel driver alucerop
2025-02-05 21:42 ` Ira Weiny
2025-02-06 17:58 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 08/26] sfc: set cxl media ready alucerop
2025-02-05 15:19 ` [PATCH v10 09/26] cxl: support device identification without mailbox alucerop
2025-02-05 21:45 ` Ira Weiny [this message]
2025-02-06 18:10 ` Alejandro Lucero Palau
2025-02-06 19:23 ` Ira Weiny
2025-02-17 13:41 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 10/26] cxl: modify dpa setup process for supporting type2 alucerop
2025-02-05 15:19 ` [PATCH v10 11/26] sfc: initialize dpa resources alucerop
2025-02-05 15:19 ` [PATCH v10 12/26] cxl: prepare memdev creation for type2 alucerop
2025-02-05 15:19 ` [PATCH v10 13/26] sfc: create type2 cxl memdev alucerop
2025-02-05 15:19 ` [PATCH v10 14/26] cxl: define a driver interface for HPA free space enumeration alucerop
2025-02-07 12:55 ` Simon Horman
2025-02-17 13:44 ` Alejandro Lucero Palau
2025-02-13 4:08 ` Alison Schofield
2025-02-17 13:49 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 15/26] sfc: obtain root decoder with enough HPA free space alucerop
2025-02-05 22:47 ` Ira Weiny
2025-02-17 13:54 ` Alejandro Lucero Palau
2025-02-18 0:03 ` Ira Weiny
2025-02-05 15:19 ` [PATCH v10 16/26] cxl: define a driver interface for DPA allocation alucerop
2025-02-06 19:11 ` kernel test robot
2025-02-07 13:46 ` Simon Horman
2025-02-17 14:08 ` Alejandro Lucero Palau
2025-02-18 13:34 ` Simon Horman
2025-02-18 14:09 ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 17/26] sfc: get endpoint decoder alucerop
2025-02-05 15:19 ` [PATCH v10 18/26] cxl: make region type based on endpoint type alucerop
2025-02-05 15:19 ` [PATCH v10 19/26] cxl/region: factor out interleave ways setup alucerop
2025-02-05 15:19 ` [PATCH v10 20/26] cxl/region: factor out interleave granularity setup alucerop
2025-02-05 15:19 ` [PATCH v10 21/26] cxl: allow region creation by type2 drivers alucerop
2025-02-06 20:06 ` kernel test robot
2025-02-07 13:23 ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 22/26] cxl: add region flag for precluding a device memory to be used for dax alucerop
2025-02-05 15:19 ` [PATCH v10 23/26] sfc: create cxl region alucerop
2025-02-05 15:19 ` [PATCH v10 24/26] cxl: add function for obtaining region range alucerop
2025-02-05 15:19 ` [PATCH v10 25/26] sfc: update MCDI protocol headers alucerop
2025-02-05 15:19 ` [PATCH v10 26/26] sfc: support pio mapping based on cxl alucerop
2025-02-13 1:51 ` [PATCH v10 00/26] cxl: add type2 device basic support Alison Schofield
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