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From: Dan Williams <dan.j.williams@intel.com>
To: <alucerop@amd.com>, <linux-cxl@vger.kernel.org>,
	<netdev@vger.kernel.org>, <dan.j.williams@intel.com>,
	<edward.cree@amd.com>, <davem@davemloft.net>, <kuba@kernel.org>,
	<pabeni@redhat.com>, <edumazet@google.com>,
	<dave.jiang@intel.com>
Cc: Alejandro Lucero <alucerop@amd.com>
Subject: Re: [PATCH v10 01/26] cxl: make memdev creation type agnostic
Date: Thu, 6 Feb 2025 11:37:35 -0800	[thread overview]
Message-ID: <67a50f7fbdfb_2d2c29447@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <20250205151950.25268-2-alucerop@amd.com>

alucerop@ wrote:
> From: Alejandro Lucero <alucerop@amd.com>
> 
> In preparation for Type2 support, change memdev creation making
> type based on argument.
> 
> Integrate initialization of dvsec and serial fields in the related
> cxl_dev_state within same function creating the memdev.
> 
> Move the code from mbox file to memdev file.
> 
> Add new header files with type2 required definitions for memdev
> state creation.
> 
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> ---
>  drivers/cxl/core/mbox.c   | 20 --------------------
>  drivers/cxl/core/memdev.c | 23 +++++++++++++++++++++++
>  drivers/cxl/cxlmem.h      | 18 +++---------------
>  drivers/cxl/cxlpci.h      | 17 +----------------
>  drivers/cxl/pci.c         | 16 +++++++++-------
>  include/cxl/cxl.h         | 26 ++++++++++++++++++++++++++
>  include/cxl/pci.h         | 23 +++++++++++++++++++++++
>  7 files changed, 85 insertions(+), 58 deletions(-)
>  create mode 100644 include/cxl/cxl.h
>  create mode 100644 include/cxl/pci.h
> 
> diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
> index 4d22bb731177..96155b8af535 100644
> --- a/drivers/cxl/core/mbox.c
> +++ b/drivers/cxl/core/mbox.c
> @@ -1435,26 +1435,6 @@ int cxl_mailbox_init(struct cxl_mailbox *cxl_mbox, struct device *host)
>  }
>  EXPORT_SYMBOL_NS_GPL(cxl_mailbox_init, "CXL");
>  
> -struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev)
> -{
> -	struct cxl_memdev_state *mds;
> -
> -	mds = devm_kzalloc(dev, sizeof(*mds), GFP_KERNEL);
> -	if (!mds) {
> -		dev_err(dev, "No memory available\n");
> -		return ERR_PTR(-ENOMEM);
> -	}
> -
> -	mutex_init(&mds->event.log_lock);
> -	mds->cxlds.dev = dev;
> -	mds->cxlds.reg_map.host = dev;
> -	mds->cxlds.reg_map.resource = CXL_RESOURCE_NONE;
> -	mds->cxlds.type = CXL_DEVTYPE_CLASSMEM;
> -
> -	return mds;
> -}
> -EXPORT_SYMBOL_NS_GPL(cxl_memdev_state_create, "CXL");
> -
>  void __init cxl_mbox_init(void)
>  {
>  	struct dentry *mbox_debugfs;
> diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
> index 63c6c681125d..456d505f1bc8 100644
> --- a/drivers/cxl/core/memdev.c
> +++ b/drivers/cxl/core/memdev.c
> @@ -632,6 +632,29 @@ static void detach_memdev(struct work_struct *work)
>  
>  static struct lock_class_key cxl_memdev_key;
>  
> +struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev, u64 serial,
> +						 u16 dvsec, enum cxl_devtype type)
> +{
> +	struct cxl_memdev_state *mds;
> +
> +	mds = devm_kzalloc(dev, sizeof(*mds), GFP_KERNEL);
> +	if (!mds) {
> +		dev_err(dev, "No memory available\n");
> +		return ERR_PTR(-ENOMEM);
> +	}
> +
> +	mutex_init(&mds->event.log_lock);
> +	mds->cxlds.dev = dev;
> +	mds->cxlds.reg_map.host = dev;
> +	mds->cxlds.reg_map.resource = CXL_RESOURCE_NONE;
> +	mds->cxlds.cxl_dvsec = dvsec;
> +	mds->cxlds.serial = serial;
> +	mds->cxlds.type = type;
> +
> +	return mds;
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_memdev_state_create, "CXL");

I was envisioning that accelerators only consider 'struct cxl_dev_state'
and that 'struct cxl_memdev_state' is exclusively for
CXL_DEVTYPE_CLASSMEM memory expander use case. Something roughly like
the below. Note, this borrows from the fwctl_alloc_device() example
which captures the spirit of registering a core object wrapped by an end
driver provided structure).

#define cxl_dev_state_create(parent, serial, dvsec, type, drv_struct, member)  \
        ({                                                                     \
                static_assert(__same_type(struct cxl_dev_state,                \
                                          ((drv_struct *)NULL)->member));      \
                static_assert(offsetof(drv_struct, member) == 0);              \
                (drv_struct *)_cxl_dev_state_create(parent, serial, dvsec,     \
                                                    type, sizeof(drv_struct)); \
        })

struct cxl_memdev_state *cxl_memdev_state_create(parent, serial, dvsec)
{
        struct cxl_memdev_state *mds = cxl_dev_state_create(
                parent, serial, dvsec, CXL_DEVTYPE_CLASSMEM,
                struct cxl_memdev_state, cxlds);

        if (IS_ERR(mds))
                return mds;
        
        mutex_init(&mds->event.log_lock);
        mds->cxlds.dev = dev;
        mds->cxlds.reg_map.host = dev;
        mds->cxlds.reg_map.resource = CXL_RESOURCE_NONE;
        mds->cxlds.cxl_dvsec = dvsec;
        mds->cxlds.serial = serial;
        mds->cxlds.type = type;

        return mds;
}

If an accelerator wants to share infrastructure that is currently housed
in 'struct cxl_memdev_state', then that functionality should first move
to 'struct cxl_dev_state'.

  reply	other threads:[~2025-02-06 19:37 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-05 15:19 [PATCH v10 00/26] cxl: add type2 device basic support alucerop
2025-02-05 15:19 ` [PATCH v10 01/26] cxl: make memdev creation type agnostic alucerop
2025-02-06 19:37   ` Dan Williams [this message]
2025-02-17 12:32     ` Alejandro Lucero Palau
2025-02-19  2:29       ` Dan Williams
2025-02-20 18:17         ` Alejandro Lucero Palau
2025-02-17 13:05     ` Alejandro Lucero Palau
2025-02-13  3:57   ` Alison Schofield
2025-02-17 12:49     ` Alejandro Lucero Palau
2025-02-17 13:06     ` Alejandro Lucero Palau
2025-02-14 17:02   ` Jonathan Cameron
2025-02-17 13:08     ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 02/26] sfc: add basic cxl initialization alucerop
2025-02-06  1:37   ` Edward Cree
2025-02-07 12:48   ` Simon Horman
2025-02-17 13:10     ` Alejandro Lucero Palau
2025-02-07 13:03   ` Simon Horman
2025-02-17 13:11     ` Alejandro Lucero Palau
2025-02-18 13:32       ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 03/26] cxl: move pci generic code alucerop
2025-02-05 21:33   ` Ira Weiny
2025-02-06 17:49     ` Alejandro Lucero Palau
2025-02-14 17:11       ` Jonathan Cameron
2025-02-17 13:13         ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 04/26] cxl: move register/capability check to driver alucerop
2025-02-07 12:52   ` Simon Horman
2025-02-17 13:17     ` Alejandro Lucero Palau
2025-02-14 17:21   ` Jonathan Cameron
2025-02-17 13:18     ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 05/26] cxl: add function for type2 cxl regs setup alucerop
2025-02-05 21:35   ` Ira Weiny
2025-02-06 17:50     ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 06/26] sfc: use cxl api for regs setup and checking alucerop
2025-02-05 21:31   ` Ira Weiny
2025-02-06 17:47     ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 07/26] cxl: add support for setting media ready by an accel driver alucerop
2025-02-05 21:42   ` Ira Weiny
2025-02-06 17:58     ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 08/26] sfc: set cxl media ready alucerop
2025-02-05 15:19 ` [PATCH v10 09/26] cxl: support device identification without mailbox alucerop
2025-02-05 21:45   ` Ira Weiny
2025-02-06 18:10     ` Alejandro Lucero Palau
2025-02-06 19:23       ` Ira Weiny
2025-02-17 13:41         ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 10/26] cxl: modify dpa setup process for supporting type2 alucerop
2025-02-05 15:19 ` [PATCH v10 11/26] sfc: initialize dpa resources alucerop
2025-02-05 15:19 ` [PATCH v10 12/26] cxl: prepare memdev creation for type2 alucerop
2025-02-05 15:19 ` [PATCH v10 13/26] sfc: create type2 cxl memdev alucerop
2025-02-05 15:19 ` [PATCH v10 14/26] cxl: define a driver interface for HPA free space enumeration alucerop
2025-02-07 12:55   ` Simon Horman
2025-02-17 13:44     ` Alejandro Lucero Palau
2025-02-13  4:08   ` Alison Schofield
2025-02-17 13:49     ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 15/26] sfc: obtain root decoder with enough HPA free space alucerop
2025-02-05 22:47   ` Ira Weiny
2025-02-17 13:54     ` Alejandro Lucero Palau
2025-02-18  0:03       ` Ira Weiny
2025-02-05 15:19 ` [PATCH v10 16/26] cxl: define a driver interface for DPA allocation alucerop
2025-02-06 19:11   ` kernel test robot
2025-02-07 13:46   ` Simon Horman
2025-02-17 14:08     ` Alejandro Lucero Palau
2025-02-18 13:34       ` Simon Horman
2025-02-18 14:09         ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 17/26] sfc: get endpoint decoder alucerop
2025-02-05 15:19 ` [PATCH v10 18/26] cxl: make region type based on endpoint type alucerop
2025-02-05 15:19 ` [PATCH v10 19/26] cxl/region: factor out interleave ways setup alucerop
2025-02-05 15:19 ` [PATCH v10 20/26] cxl/region: factor out interleave granularity setup alucerop
2025-02-05 15:19 ` [PATCH v10 21/26] cxl: allow region creation by type2 drivers alucerop
2025-02-06 20:06   ` kernel test robot
2025-02-07 13:23   ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 22/26] cxl: add region flag for precluding a device memory to be used for dax alucerop
2025-02-05 15:19 ` [PATCH v10 23/26] sfc: create cxl region alucerop
2025-02-05 15:19 ` [PATCH v10 24/26] cxl: add function for obtaining region range alucerop
2025-02-05 15:19 ` [PATCH v10 25/26] sfc: update MCDI protocol headers alucerop
2025-02-05 15:19 ` [PATCH v10 26/26] sfc: support pio mapping based on cxl alucerop
2025-02-13  1:51 ` [PATCH v10 00/26] cxl: add type2 device basic support Alison Schofield

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