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(93-34-90-129.ip49.fastwebnet.it. [93.34.90.129]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d4fd9decbsm160143145e9.27.2025.03.25.13.41.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Mar 2025 13:41:22 -0700 (PDT) Message-ID: <67e314f2.050a0220.f130b.7b84@mx.google.com> X-Google-Original-Message-ID: Date: Tue, 25 Mar 2025 21:41:20 +0100 From: Christian Marangi To: Andrew Lunn Cc: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [net-next PATCH 1/2] net: phy: Add support for new Aeonsemi PHYs References: <20250323225439.32400-1-ansuelsmth@gmail.com> <67e1692c.050a0220.2b4ad0.c073@mx.google.com> <67e29bce.050a0220.15db86.84a4@mx.google.com> <4f865b3a-0568-4fef-a56d-6360dfbd18f6@lunn.ch> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4f865b3a-0568-4fef-a56d-6360dfbd18f6@lunn.ch> On Tue, Mar 25, 2025 at 09:33:26PM +0100, Andrew Lunn wrote: > On Tue, Mar 25, 2025 at 01:04:30PM +0100, Christian Marangi wrote: > > On Mon, Mar 24, 2025 at 04:16:09PM +0100, Andrew Lunn wrote: > > > On Mon, Mar 24, 2025 at 03:16:08PM +0100, Christian Marangi wrote: > > > > On Mon, Mar 24, 2025 at 03:03:51PM +0100, Andrew Lunn wrote: > > > > > > Supported PHYs AS21011JB1, AS21011PB1, AS21010JB1, AS21010PB1, > > > > > > AS21511JB1, AS21511PB1, AS21510JB1, AS21510PB1, AS21210JB1, > > > > > > AS21210PB1 that all register with the PHY ID 0x7500 0x7500 > > > > > > before the firmware is loaded. > > Do you have details of how these different PHY differ? Do they have > different features? > No but I can ask more details. From what I can assume, gigabit, 2.5g 10g and probably a PHY that expose multiple port (PHY package thing) > > Ok update on this... The PHY report 7500 7500 but on enabling PTP clock, > > a more specific ""family"" ID is filled in MMD that is 0x7500 0x9410. > > Do they all support PTP? > With PTP it's not the PTP we think but I guess it's something internal to the PHY to actually start it. From comments it's called PTP Clock... > > They all use the same firmware so matching for the family ID might not > > be a bad idea... The alternative is either load the firmware in > > match_phy_device or introduce some additional OPs to handle this > > correctly... > > > > Considering how the thing are evolving with PHY I really feel it's time > > we start introducing specific OP for firmware loading and we might call > > this OP before PHY ID matching is done (or maybe do it again). > > You cannot download firmware before doing some sort of match, because > you have no idea what PHY you actually have until you do a match, and > if the PHY needs firmware. > > match_phy_device() gives you a bit more flexibility. It will be called > for every PHY on the board, independent of the ID registers. So you > can read the ID registers, see if it is at least a vendor you know how > to download firmware to, do the download, and then look at the ID > registers again to see if it is the version of the PHY you want to > drive. If not, return -ENODEV, and the core will try the next driver > entry. > I'm finishing preparing V2 and I'm curious what you will think of the implementation. The approach I found works good is permit PHY device to register a second time and the PHY driver toggle this. This way in a PHY driver we register OPs for the to-be-init PHY and then we probe the real one. -- Ansuel