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From: Dan Williams <dan.j.williams@intel.com>
To: <alejandro.lucero-palau@amd.com>, <linux-cxl@vger.kernel.org>,
	<netdev@vger.kernel.org>, <dan.j.williams@intel.com>,
	<edward.cree@amd.com>, <davem@davemloft.net>, <kuba@kernel.org>,
	<pabeni@redhat.com>, <edumazet@google.com>,
	<dave.jiang@intel.com>
Cc: Alejandro Lucero <alucerop@amd.com>,
	Martin Habets <habetsm.xilinx@gmail.com>,
	Zhi Wang <zhi@nvidia.com>, Edward Cree <ecree.xilinx@gmail.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	"Ben Cheatham" <benjamin.cheatham@amd.com>
Subject: Re: [PATCH v16 06/22] sfc: make regs setup with checking and set media ready
Date: Wed, 21 May 2025 11:34:54 -0700	[thread overview]
Message-ID: <682e1ccec6ebf_1626e1009a@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <20250514132743.523469-7-alejandro.lucero-palau@amd.com>

alejandro.lucero-palau@ wrote:
> From: Alejandro Lucero <alucerop@amd.com>
> 
> Use cxl code for registers discovery and mapping.
> 
> Validate capabilities found based on those registers against expected
> capabilities.
> 
> Set media ready explicitly as there is no means for doing so without
> a mailbox and without the related cxl register, not mandatory for type2.
> 
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> Reviewed-by: Martin Habets <habetsm.xilinx@gmail.com>
> Reviewed-by: Zhi Wang <zhi@nvidia.com>
> Acked-by: Edward Cree <ecree.xilinx@gmail.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
> ---
>  drivers/net/ethernet/sfc/efx_cxl.c | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c
> index 753d5b7d49b6..e94af8bf3a79 100644
> --- a/drivers/net/ethernet/sfc/efx_cxl.c
> +++ b/drivers/net/ethernet/sfc/efx_cxl.c
> @@ -19,10 +19,13 @@
>  
>  int efx_cxl_init(struct efx_probe_data *probe_data)
>  {
> +	DECLARE_BITMAP(expected, CXL_MAX_CAPS) = {};
> +	DECLARE_BITMAP(found, CXL_MAX_CAPS) = {};
>  	struct efx_nic *efx = &probe_data->efx;
>  	struct pci_dev *pci_dev = efx->pci_dev;
>  	struct efx_cxl *cxl;
>  	u16 dvsec;
> +	int rc;
>  
>  	probe_data->cxl_pio_initialised = false;
>  
> @@ -43,6 +46,29 @@ int efx_cxl_init(struct efx_probe_data *probe_data)
>  	if (!cxl)
>  		return -ENOMEM;
>  
> +	set_bit(CXL_DEV_CAP_HDM, expected);
> +	set_bit(CXL_DEV_CAP_RAS, expected);
> +
> +	rc = cxl_pci_accel_setup_regs(pci_dev, &cxl->cxlds, found);
> +	if (rc) {
> +		pci_err(pci_dev, "CXL accel setup regs failed");
> +		return rc;
> +	}
> +
> +	/*
> +	 * Checking mandatory caps are there as, at least, a subset of those
> +	 * found.
> +	 */
> +	if (cxl_check_caps(pci_dev, expected, found))
> +		return -ENXIO;

This all looks like an obfuscated way of writing:

    cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map);
    if (!map.component_map.ras.valid || !map.component_map.hdm_decoder.valid)
         /* sfc cxl expectations not met */

  reply	other threads:[~2025-05-21 18:35 UTC|newest]

Thread overview: 84+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-14 13:27 [PATCH v16 00/22] Type2 device basic support alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 01/22] cxl: Add type2 " alejandro.lucero-palau
2025-05-20  2:43   ` Alison Schofield
2025-05-20  7:18     ` Alejandro Lucero Palau
2025-05-20 20:06       ` Dave Jiang
2025-05-21  9:30         ` Alejandro Lucero Palau
2025-05-20  7:17   ` dan.j.williams
2025-05-21 10:44     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 02/22] sfc: add cxl support alejandro.lucero-palau
2025-05-20  7:37   ` dan.j.williams
2025-05-21 10:50     ` Alejandro Lucero Palau
2025-05-21 17:12       ` Dan Williams
2025-05-22  8:49         ` Alejandro Lucero Palau
2025-05-22 19:41           ` Dan Williams
2025-06-04  8:09             ` Jonathan Cameron
2025-05-14 13:27 ` [PATCH v16 03/22] cxl: Move pci generic code alejandro.lucero-palau
2025-05-20  2:42   ` Alison Schofield
2025-05-21 17:44   ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 04/22] cxl: Move register/capability check to driver alejandro.lucero-palau
2025-05-20  2:41   ` Alison Schofield
2025-05-21 18:23   ` Dan Williams
2025-05-22  9:45     ` Alejandro Lucero Palau
2025-05-22 19:51       ` Dan Williams
2025-05-23  9:12         ` Alejandro Lucero Palau
2025-05-23 16:55           ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 05/22] cxl: Add function for type2 cxl regs setup alejandro.lucero-palau
2025-05-20  2:41   ` Alison Schofield
2025-05-21 18:28   ` Dan Williams
2025-05-22  9:52     ` Alejandro Lucero Palau
2025-05-22 20:04       ` Dan Williams
2025-06-06 11:59         ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 06/22] sfc: make regs setup with checking and set media ready alejandro.lucero-palau
2025-05-21 18:34   ` Dan Williams [this message]
2025-05-22 10:07     ` Alejandro Lucero Palau
2025-05-22 20:22       ` Dan Williams
2025-05-22 20:53         ` Dan Williams
2025-05-22 21:09           ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 07/22] cxl: Support dpa initialization without a mailbox alejandro.lucero-palau
2025-05-20  2:40   ` Alison Schofield
2025-05-21 18:47   ` Dan Williams
2025-05-22 10:24     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 08/22] sfc: initialize dpa alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 09/22] cxl: Prepare memdev creation for type2 alejandro.lucero-palau
2025-05-20  2:40   ` Alison Schofield
2025-05-21 18:49   ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 10/22] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 11/22] cxl: Define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-05-20  2:36   ` Alison Schofield
2025-05-21 19:31   ` Dan Williams
2025-05-22 10:56     ` Alejandro Lucero Palau
2025-05-22 20:31       ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 12/22] sfc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2025-05-21 19:56   ` Dan Williams
2025-06-06 12:59     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 13/22] cxl: Define a driver interface for DPA allocation alejandro.lucero-palau
2025-05-20  2:39   ` Alison Schofield
2025-05-21 20:23   ` Dan Williams
2025-06-06 13:09     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 14/22] sfc: get endpoint decoder alejandro.lucero-palau
2025-05-21 20:28   ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 15/22] cxl: Make region type based on endpoint type alejandro.lucero-palau
2025-05-20  2:39   ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 16/22] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2025-05-20  2:37   ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 17/22] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2025-05-20  2:38   ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 18/22] cxl: Allow region creation by type2 drivers alejandro.lucero-palau
2025-05-20  2:37   ` Alison Schofield
2025-05-21 20:45   ` Dan Williams
2025-06-06 13:27     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 19/22] cxl: Add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2025-05-20  2:36   ` Alison Schofield
2025-05-21 20:49   ` Dan Williams
2025-06-06 13:39     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 20/22] sfc: create cxl region alejandro.lucero-palau
2025-05-21 21:01   ` Dan Williams
2025-06-06 13:44     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 21/22] cxl: Add function for obtaining region range alejandro.lucero-palau
2025-05-20  2:35   ` Alison Schofield
2025-05-21 21:31   ` Dan Williams
2025-06-06 14:03     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 22/22] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-05-21 21:48   ` Dan Williams
2025-05-23  1:13     ` Edward Cree

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