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Wed, 21 May 2025 20:45:50 +0000 Date: Wed, 21 May 2025 13:45:48 -0700 From: Dan Williams To: , , , , , , , , , CC: Alejandro Lucero , Jonathan Cameron Subject: Re: [PATCH v16 18/22] cxl: Allow region creation by type2 drivers Message-ID: <682e3b7cf2b2_1626e100ce@dwillia2-xfh.jf.intel.com.notmuch> References: <20250514132743.523469-1-alejandro.lucero-palau@amd.com> <20250514132743.523469-19-alejandro.lucero-palau@amd.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20250514132743.523469-19-alejandro.lucero-palau@amd.com> X-ClientProxiedBy: BY5PR20CA0014.namprd20.prod.outlook.com (2603:10b6:a03:1f4::27) To PH8PR11MB8107.namprd11.prod.outlook.com (2603:10b6:510:256::6) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8107:EE_|SA1PR11MB8393:EE_ X-MS-Office365-Filtering-Correlation-Id: c2c7e902-c8b1-45f7-1c43-08dd98a8786f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|376014|7416014|921020; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?8616v5eiHzhmiksYdr9UNtJFjR46TOfcN4M8dGsgmxaWSOogbbTkx/mCOjF7?= =?us-ascii?Q?OOkwTOya4cxXrx/vDLm2wtJljC3GmFIUpC+n1wtPAiWoox896+lh5sMNgF8R?= =?us-ascii?Q?uIi6h9Kp1fR3LLpshGkPM6jrWAJvtDMmD3WQkxBCLEYz7dD56X3ojwk57Pv5?= =?us-ascii?Q?dw8CTu6ePhToIIjwDQKtp653wvQkRuAS/i6jyHhzNcJP0YhOy9iOMt8p46an?= =?us-ascii?Q?IkfTyQkMR2+QPZYczdvub15HlLhfDzB4ILnI1JNtSWRb1djie1WKDNNSdI7h?= =?us-ascii?Q?XBxQK7fjSWiUAgGPv0sOnnat7YaUjIdo8hRoavxe/Mygld7ZZmODjQxt/OiK?= =?us-ascii?Q?3OocXVvDxD8qGIa0WXGOfXOmahEAiKyRLuLA5psAcjh+23wHNYfkYjuZWCJW?= =?us-ascii?Q?oSFYsjEVENCpN1z2nMlEuouKeYzWEHfcIiu6kVPU2vu7EMDXHDAW6DOuzl5H?= =?us-ascii?Q?Lgi7SYxFbLcIk6lG0Sl0fekUo3waodD7Wgixn19s3M2sDB+biteUJWianCO4?= =?us-ascii?Q?1n7IlX5QKmCydK6lx8NjrvVaBDFuPryEXFw0/PqvuJHPyv6gdPSNFMqZgimd?= =?us-ascii?Q?elQUsUgf9FY4QCHi+QeUhKN6GNBbBV0N3datJFfdurkvEabbRvYC9TdkicH9?= =?us-ascii?Q?Kw63H66ae6AwehiLxO4atUgEjWrloJk8nxt1Mx+oZitgJ6FPKL1gS28uvtwW?= =?us-ascii?Q?p77nlRCLTvGszWNur9vDZBogalc3QwnAcDZADar0Nij11B06kVH2ZMgzqVCn?= =?us-ascii?Q?c1Qlk69AulB0DOgSXvPPFIqnyXUI6jJy9dV3BX/GdDi/B94zDc+DAqBoeABY?= =?us-ascii?Q?cC9rpQYYi+5vJOzSl01sjEMQy2o3RmOBLYxgJmUf2SORPeLlX2fUJMte64QE?= =?us-ascii?Q?o2stARqVs+RzMBK2BV6ZVGKWp7/whIJ1qIWBTbRj52CpIkpAnE8u2+2qtisx?= =?us-ascii?Q?8272xCHGaTbsXZTpvcf4XTTCTkUvIBKHYGkb+EOpG6vlDWN0dY5+TYekPx8g?= =?us-ascii?Q?ZGqQSBKLyt6kfUdFD9BXv5Wu/FLOwOKySS0Fch3VG8gx94wPrl2vsbJ3SzOB?= =?us-ascii?Q?u161e3wAX+ecvO4FYRuaiK3FQQ8niCMOD1n0B3EJr+pUDsUO33n8qhoWe2sb?= =?us-ascii?Q?vlYnNHpOV1nuYUKM7EAbAbJAlxQR0LyfDPzSGzKZ9eJM48mCOoBd50uL3vSI?= =?us-ascii?Q?TUXdbKLOrqZi93Mcq+jcLhEnBT8LoEsIgZyP4E6qftij/UrZCSPhi/FIdpub?= =?us-ascii?Q?ecVlW9af6mcp8IxAtVq9qtStcIen+m0+ws0A56J+4V4qQ0LMDbYk8t34ctjh?= =?us-ascii?Q?CPFQUd6oLYh0Zixtrii3pddN/irR+fpbnEKjmyO6dXyOKB+oqAmU7+SrcTpU?= =?us-ascii?Q?0jpkAVXxwdnikSczOO0xuu+wUiegmUNtMudNe5F7T2qcWDyB1Cntd5URP5Uh?= =?us-ascii?Q?10zrt4nCCb+O8lHaZKEfbw4fai+zpQ1pB6+GKZa3fhQCGifAGwxCbXfhTa/1?= =?us-ascii?Q?45nsmmclVyEPHjunaOOilf60Ou9x4hBrGWqlSOvBz2CKWOfYBkidzRfgnv+g?= =?us-ascii?Q?Gab3aJ0uhoqdsxJT75n2DHmlLNDEoO9gkfCE8S92W5CIlEqp8Jr8fvhVYbVy?= =?us-ascii?Q?MQ=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: c2c7e902-c8b1-45f7-1c43-08dd98a8786f X-MS-Exchange-CrossTenant-AuthSource: PH8PR11MB8107.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2025 20:45:50.0465 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: GvIdPC/MAulbi8YNcjcbDHW+W2AtK2YcqutSvnMXTqGzvIKbG8gMXU2qXWF5DN9l/wTNdD3Tc6noD0Un33ekMRpw8HSBbhl+QF2LS+MAMSY= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR11MB8393 X-OriginatorOrg: intel.com alejandro.lucero-palau@ wrote: > From: Alejandro Lucero > > Creating a CXL region requires userspace intervention through the cxl > sysfs files. Type2 support should allow accelerator drivers to create > such cxl region from kernel code. > > Adding that functionality and integrating it with current support for > memory expanders. > > Based on https://lore.kernel.org/linux-cxl/168592159835.1948938.1647215579839222774.stgit@dwillia2-xfh.jf.intel.com/ > > Signed-off-by: Alejandro Lucero > Reviewed-by: Jonathan Cameron > --- > drivers/cxl/core/region.c | 140 +++++++++++++++++++++++++++++++++++--- > drivers/cxl/port.c | 5 +- > include/cxl/cxl.h | 4 ++ > 3 files changed, 140 insertions(+), 9 deletions(-) > > diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c > index 4113ee6daec9..f82da914d125 100644 > --- a/drivers/cxl/core/region.c > +++ b/drivers/cxl/core/region.c > @@ -2316,6 +2316,21 @@ static int cxl_region_detach(struct cxl_endpoint_decoder *cxled) > return rc; > } > > +/** > + * cxl_accel_region_detach - detach a region from a Type2 device > + * > + * @cxled: Type2 endpoint decoder to detach the region from. > + * > + * Returns 0 or error. > + */ > +int cxl_accel_region_detach(struct cxl_endpoint_decoder *cxled) > +{ > + guard(rwsem_write)(&cxl_region_rwsem); > + cxled->part = -1; > + return cxl_region_detach(cxled); > +} > +EXPORT_SYMBOL_NS_GPL(cxl_accel_region_detach, "CXL"); There's nothing "accel" about the above sequence, it is nearly identical to cxl_decoder_kill_region(). In general there does not need to be a parallel universe of "cxl_accel_" helpers for Type-2, just use existing infrastructure and maybe enlighten it a bit to accommodate a Type-2 nuance. > + > void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled) > { > down_write(&cxl_region_rwsem); > @@ -2822,6 +2837,14 @@ cxl_find_region_by_name(struct cxl_root_decoder *cxlrd, const char *name) > return to_cxl_region(region_dev); > } > > +static void drop_region(struct cxl_region *cxlr) > +{ > + struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent); > + struct cxl_port *port = cxlrd_to_port(cxlrd); > + > + devm_release_action(port->uport_dev, unregister_region, cxlr); > +} > + > static ssize_t delete_region_store(struct device *dev, > struct device_attribute *attr, > const char *buf, size_t len) > @@ -3526,14 +3549,12 @@ static int __construct_region(struct cxl_region *cxlr, > return 0; > } > > -/* Establish an empty region covering the given HPA range */ > -static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd, > - struct cxl_endpoint_decoder *cxled) > +static struct cxl_region *construct_region_begin(struct cxl_root_decoder *cxlrd, > + struct cxl_endpoint_decoder *cxled) > { > struct cxl_memdev *cxlmd = cxled_to_memdev(cxled); > - struct cxl_port *port = cxlrd_to_port(cxlrd); > struct cxl_dev_state *cxlds = cxlmd->cxlds; > - int rc, part = READ_ONCE(cxled->part); > + int part = READ_ONCE(cxled->part); > struct cxl_region *cxlr; > > do { > @@ -3542,13 +3563,23 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd, > cxled->cxld.target_type); > } while (IS_ERR(cxlr) && PTR_ERR(cxlr) == -EBUSY); > > - if (IS_ERR(cxlr)) { > + if (IS_ERR(cxlr)) > dev_err(cxlmd->dev.parent, > "%s:%s: %s failed assign region: %ld\n", > dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), > __func__, PTR_ERR(cxlr)); > - return cxlr; > - } > + return cxlr; > +}; > + > +/* Establish an empty region covering the given HPA range */ > +static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd, > + struct cxl_endpoint_decoder *cxled) > +{ > + struct cxl_port *port = cxlrd_to_port(cxlrd); > + struct cxl_region *cxlr; > + int rc; > + > + cxlr = construct_region_begin(cxlrd, cxled); > > rc = __construct_region(cxlr, cxlrd, cxled); > if (rc) { > @@ -3559,6 +3590,99 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd, > return cxlr; > } > > +static struct cxl_region * > +__construct_new_region(struct cxl_root_decoder *cxlrd, > + struct cxl_endpoint_decoder *cxled, int ways) What is the point of an @ways argument when @cxled is not an array? It was an array in the original proposal. Recall that this interface needs to be useful not only to Type-2 but also the nascent CXL PMEM case which will likely need to create interleave CXL PMEM regions from label data.