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From: Dan Williams <dan.j.williams@intel.com>
To: Alejandro Lucero Palau <alucerop@amd.com>,
	Dan Williams <dan.j.williams@intel.com>,
	<alejandro.lucero-palau@amd.com>, <linux-cxl@vger.kernel.org>,
	<netdev@vger.kernel.org>, <edward.cree@amd.com>,
	<davem@davemloft.net>, <kuba@kernel.org>, <pabeni@redhat.com>,
	<edumazet@google.com>, <dave.jiang@intel.com>
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Edward Cree <ecree.xilinx@gmail.com>
Subject: Re: [PATCH v16 02/22] sfc: add cxl support
Date: Thu, 22 May 2025 12:41:19 -0700	[thread overview]
Message-ID: <682f7ddf1f0b9_3e70100fb@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <8a993411-26db-44c6-954c-e58eb12f9d82@amd.com>

Alejandro Lucero Palau wrote:
> 
> On 5/21/25 18:12, Dan Williams wrote:
> > Alejandro Lucero Palau wrote:
> > [..]
> >>>> +void efx_cxl_exit(struct efx_probe_data *probe_data)
> >>>> +{
> >>> So this is empty which means it leaks the cxl_dev_state_create()
> >>> allocation, right?
> >>
> >> Yes, because I was wrongly relying on devres ...
> >>
> >>
> >> Previous patchsets were doing the explicit release here.
> >>
> >>
> >> Your suggestion below relies on adding more awareness of cxl into
> >> generic efx code, what we want to avoid using the specific efx_cxl.* files.
> >>
> >> As I mentioned in patch 1, I think the right thing to do is to add
> >> devres for cxl_dev_state_create.
> > ...but I thought netdev is anti-devres? I am ok having a
> > devm_cxl_dev_state_create() alongside a "manual" cxl_dev_state_create()
> > if that is the case.
> 
> 
> But a netdev is using the CXL API where devres is being used already. 
> AFAIK, netdev maintainers prefer to not use devres by netdev drivers, 
> but I do not think they can impose their view to external API, mainly 
> when other driver types could likely also make use of it in the future.

From the CXL perspective I am neutral. As long as the parallel manual
interfaces arrange to undo everything it "should just work (TM)". You
would need to create the manual version of devm_cxl_add_memdev(), and
audit that the paired cxl_del_memdev() does not result in any cxl_core
internal devres events to leak past the ->remove() event for the
accelerator driver.

> >> Before sending v17 with this change, are you ok with the rest of the
> >> patches or you want to go through them as well?
> > So I did start taking a look and then turned away upon finding a
> > memory-leak on the first 2 patches in the series. I will continue going
> > through it, but in general the lifetime and locking rules of the CXL
> > subsystem continue to be a source of trouble in new enabling. At a
> > minimum that indicates a need/opportunity to review the rules at a
> > future CXL collab meeting.
> 
> Great. And I agree about potential improvements mostly required after 
> all this new code (hopefully) ends up being merged, which I'll be happy 
> to contribute. Also, note this patchset original RFC and  cover letters 
> since then states "basic Type2 support".

It would help to define "basic" in terms of impact. How much end-user
benefit arrives at this stage, and what is driving motivation to go
beyond basic. E.g. "PIO buffer in CXL == X amount of goodness, and Y
amount of goodness comes with additional changes".

  reply	other threads:[~2025-05-22 19:42 UTC|newest]

Thread overview: 84+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-14 13:27 [PATCH v16 00/22] Type2 device basic support alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 01/22] cxl: Add type2 " alejandro.lucero-palau
2025-05-20  2:43   ` Alison Schofield
2025-05-20  7:18     ` Alejandro Lucero Palau
2025-05-20 20:06       ` Dave Jiang
2025-05-21  9:30         ` Alejandro Lucero Palau
2025-05-20  7:17   ` dan.j.williams
2025-05-21 10:44     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 02/22] sfc: add cxl support alejandro.lucero-palau
2025-05-20  7:37   ` dan.j.williams
2025-05-21 10:50     ` Alejandro Lucero Palau
2025-05-21 17:12       ` Dan Williams
2025-05-22  8:49         ` Alejandro Lucero Palau
2025-05-22 19:41           ` Dan Williams [this message]
2025-06-04  8:09             ` Jonathan Cameron
2025-05-14 13:27 ` [PATCH v16 03/22] cxl: Move pci generic code alejandro.lucero-palau
2025-05-20  2:42   ` Alison Schofield
2025-05-21 17:44   ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 04/22] cxl: Move register/capability check to driver alejandro.lucero-palau
2025-05-20  2:41   ` Alison Schofield
2025-05-21 18:23   ` Dan Williams
2025-05-22  9:45     ` Alejandro Lucero Palau
2025-05-22 19:51       ` Dan Williams
2025-05-23  9:12         ` Alejandro Lucero Palau
2025-05-23 16:55           ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 05/22] cxl: Add function for type2 cxl regs setup alejandro.lucero-palau
2025-05-20  2:41   ` Alison Schofield
2025-05-21 18:28   ` Dan Williams
2025-05-22  9:52     ` Alejandro Lucero Palau
2025-05-22 20:04       ` Dan Williams
2025-06-06 11:59         ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 06/22] sfc: make regs setup with checking and set media ready alejandro.lucero-palau
2025-05-21 18:34   ` Dan Williams
2025-05-22 10:07     ` Alejandro Lucero Palau
2025-05-22 20:22       ` Dan Williams
2025-05-22 20:53         ` Dan Williams
2025-05-22 21:09           ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 07/22] cxl: Support dpa initialization without a mailbox alejandro.lucero-palau
2025-05-20  2:40   ` Alison Schofield
2025-05-21 18:47   ` Dan Williams
2025-05-22 10:24     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 08/22] sfc: initialize dpa alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 09/22] cxl: Prepare memdev creation for type2 alejandro.lucero-palau
2025-05-20  2:40   ` Alison Schofield
2025-05-21 18:49   ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 10/22] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 11/22] cxl: Define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-05-20  2:36   ` Alison Schofield
2025-05-21 19:31   ` Dan Williams
2025-05-22 10:56     ` Alejandro Lucero Palau
2025-05-22 20:31       ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 12/22] sfc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2025-05-21 19:56   ` Dan Williams
2025-06-06 12:59     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 13/22] cxl: Define a driver interface for DPA allocation alejandro.lucero-palau
2025-05-20  2:39   ` Alison Schofield
2025-05-21 20:23   ` Dan Williams
2025-06-06 13:09     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 14/22] sfc: get endpoint decoder alejandro.lucero-palau
2025-05-21 20:28   ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 15/22] cxl: Make region type based on endpoint type alejandro.lucero-palau
2025-05-20  2:39   ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 16/22] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2025-05-20  2:37   ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 17/22] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2025-05-20  2:38   ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 18/22] cxl: Allow region creation by type2 drivers alejandro.lucero-palau
2025-05-20  2:37   ` Alison Schofield
2025-05-21 20:45   ` Dan Williams
2025-06-06 13:27     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 19/22] cxl: Add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2025-05-20  2:36   ` Alison Schofield
2025-05-21 20:49   ` Dan Williams
2025-06-06 13:39     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 20/22] sfc: create cxl region alejandro.lucero-palau
2025-05-21 21:01   ` Dan Williams
2025-06-06 13:44     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 21/22] cxl: Add function for obtaining region range alejandro.lucero-palau
2025-05-20  2:35   ` Alison Schofield
2025-05-21 21:31   ` Dan Williams
2025-06-06 14:03     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 22/22] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-05-21 21:48   ` Dan Williams
2025-05-23  1:13     ` Edward Cree

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