From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10D0DC43381 for ; Wed, 27 Feb 2019 08:19:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D5A58218E0 for ; Wed, 27 Feb 2019 08:19:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729325AbfB0ITp (ORCPT ); Wed, 27 Feb 2019 03:19:45 -0500 Received: from relay4-d.mail.gandi.net ([217.70.183.196]:44775 "EHLO relay4-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726791AbfB0ITp (ORCPT ); Wed, 27 Feb 2019 03:19:45 -0500 X-Originating-IP: 90.88.147.150 Received: from aptenodytes (aaubervilliers-681-1-27-150.w90-88.abo.wanadoo.fr [90.88.147.150]) (Authenticated sender: paul.kocialkowski@bootlin.com) by relay4-d.mail.gandi.net (Postfix) with ESMTPSA id 1514CE0003; Wed, 27 Feb 2019 08:19:41 +0000 (UTC) Message-ID: <6962f9af94b985ecb67e0386ca69ae7096f84a6e.camel@bootlin.com> Subject: Re: Handling an Extra Signal at PHY Reset From: Paul Kocialkowski To: Andrew Lunn Cc: Florian Fainelli , Heiner Kallweit , netdev@vger.kernel.org, Thomas Petazzoni , =?ISO-8859-1?Q?Myl=E8ne?= Josserand Date: Wed, 27 Feb 2019 09:19:41 +0100 In-Reply-To: <20190221140458.GF5653@lunn.ch> References: <20190221014938.GQ14879@lunn.ch> <20190221140458.GF5653@lunn.ch> Organization: Bootlin Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.30.5 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Hi Andrew, On Thu, 2019-02-21 at 15:04 +0100, Andrew Lunn wrote: > > I can also confirm that it does not prevent contacting the PHY on the > > MDIO bus, contrary to what I have stated previously. > > O.K, so wrong voltage does not matter, you can still probe the PHY. > > Ignore the switch. Use a pin hog to set the GPIO to the disabled > state. And set the voltage using the PHY register during probe(). Thanks a lot for your suggestion! I have tried it out and it appears to work just as well as before. Although the CONFIG pin state is still sampled at PHY reset, having it connected to the PTP clock instead of the LED pin does not seem to change the address we're getting. We'll stick with that solution, since it's the least invasive one. Cheers, Paul -- Paul Kocialkowski, Bootlin Embedded Linux and kernel engineering https://bootlin.com