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(93-34-88-81.ip49.fastwebnet.it. [93.34.88.81]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-434af6b2988sm147835f8f.28.2026.01.14.08.29.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 08:29:30 -0800 (PST) Message-ID: <6967c46a.5d0a0220.1ba90b.393c@mx.google.com> X-Google-Original-Message-ID: Date: Wed, 14 Jan 2026 17:29:28 +0100 From: Christian Marangi To: Andrew Lunn Cc: Krzysztof Kozlowski , Lorenzo Bianconi , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: Re: [PATCH net-next v2 1/2] dt-bindings: net: airoha: npu: Add EN7581-7996 support References: <20260113-airoha-npu-firmware-name-v2-0-28cb3d230206@kernel.org> <20260113-airoha-npu-firmware-name-v2-1-28cb3d230206@kernel.org> <20260114-heretic-optimal-seahorse-bb094d@quoll> <75f9d8c9-20a9-4b7e-a41c-8a17c8288550@kernel.org> <69676b6c.050a0220.5afb9.88e4@mx.google.com> <69677256.5d0a0220.2dc5a5.fad0@mx.google.com> <76bbffa8-e830-4d02-a676-b494616568a2@lunn.ch> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <76bbffa8-e830-4d02-a676-b494616568a2@lunn.ch> On Wed, Jan 14, 2026 at 04:56:02PM +0100, Andrew Lunn wrote: > > > Yes. What you plug into PCI is not a part of this hardware, so cannot be > > > part of the compatible. > > > > > > > Thanks for the quick response. Just to make sure Lorenzo doesn't get > > confused, I guess a v3 would be sending v1 again (firmware-names > > implementation series) with the review tag and we should be done with > > this. > > Since this is a PCI device, you can ask it what it is, and then load > the correct firmware based on the PCI vendor:product. You don't need > to describe the hardware in DT because it is enumerable. > Hi Andrew, I think it's problematic to create a bind between the NPU and PCIe. Do you have any hint on how it's possible to read the PCI device attached? I'm not aware of any API that can be used to enumerate what pcie devices is present on the device? Considering how tightly integrated things are in this SoC I still feel firmware-names is the most effective solution for this. The WiFi offload is mostly optional and sadly due to Airoha limitation, it's not possible to have separate blob for the single feature/support. -- Ansuel