From: Paolo Abeni <pabeni@redhat.com>
To: chia-yu.chang@nokia-bell-labs.com, linyunsheng@huawei.com,
andrew+netdev@lunn.ch, parav@nvidia.com, jasowang@redhat.com,
mst@redhat.com, shenjian15@huawei.com, salil.mehta@huawei.com,
shaojijie@huawei.com, saeedm@nvidia.com, tariqt@nvidia.com,
mbloch@nvidia.com, leonro@nvidia.com, linux-rdma@vger.kernel.org,
netdev@vger.kernel.org, davem@davemloft.net, edumazet@google.com,
kuba@kernel.org, horms@kernel.org, ij@kernel.org,
ncardwell@google.com, koen.de_schepper@nokia-bell-labs.com,
g.white@cablelabs.com, ingemar.s.johansson@ericsson.com,
mirja.kuehlewind@ericsson.com, cheshire@apple.com,
rs.ietf@gmx.at, Jason_Livingood@comcast.com,
vidhi_goel@apple.com
Subject: Re: [PATCH v4 net 2/3] net: mlx5e: fix CWR handling in drivers to preserve ACE signal
Date: Thu, 23 Apr 2026 09:30:47 +0200 [thread overview]
Message-ID: <69750ae3-3b0f-41c7-9731-6d49f5f6d319@redhat.com> (raw)
In-Reply-To: <20260417152642.71674-3-chia-yu.chang@nokia-bell-labs.com>
On 4/17/26 5:26 PM, chia-yu.chang@nokia-bell-labs.com wrote:
> From: Chia-Yu Chang <chia-yu.chang@nokia-bell-labs.com>
>
> Currently, mlx5 Rx paths use the SKB_GSO_TCP_ECN flag when a TCP segment
> with the CWR flag set. This is wrong because SKB_GSO_TCP_ECN is only
> valid for RFC3168 ECN on Tx, and using it on Rx allows RFC3168 ECN
> offload to clear the CWR flag. As a result, incoming TCP segments
> may lose their ACE signal integrity required for AccECN (RFC9768),
> especially when the packet is forwarded and later re-segmented by GSO.
>
> Fix this by setting SKB_GSO_TCP_ACCECN for any Rx segment with the CWR
> flag set. SKB_GSO_TCP_ACCECN ensures that RFC3168 ECN offload will
> not clear the CWR flag, therefore preserving the ACE signal.
>
> Fixes: 92552d3abd329 ("net/mlx5e: HW_GRO cqe handler implementation")
> Signed-off-by: Chia-Yu Chang <chia-yu.chang@nokia-bell-labs.com>
> ---
> drivers/net/ethernet/mellanox/mlx5/core/en_rx.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
> index 5b60aa47c75b..9b1c80079532 100644
> --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
> +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
> @@ -1180,7 +1180,7 @@ static void mlx5e_shampo_update_ipv4_tcp_hdr(struct mlx5e_rq *rq, struct iphdr *
> skb->csum_offset = offsetof(struct tcphdr, check);
>
> if (tcp->cwr)
> - skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
> + skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ACCECN;
Here there is an open question for nVidia:
Is the above enough or will later segmentation lead to the wrong
results? I think/guess the firmware is (still) aggregating the wire
frames using the ECN schema, i.e. the first wire packet has CWR == 1,
the later CWR==0.
If so, later segmentation of this GSO packet will emit CWR == 1 on all
the packets, making the egress stream different from ingress.
@Saeed, Leon, Tariq: could you please have a look here?
I guess that with a more conservative approach drivers update should be
omitted, and the updated documentation should be less forceful (i.e.
"TCP_ECN should not be used in RX")
/P
Thanks,
Paolo
next prev parent reply other threads:[~2026-04-23 7:30 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-17 15:26 [PATCH v4 net 0/3] ECN offload handling for AccECN series chia-yu.chang
2026-04-17 15:26 ` [PATCH v4 net 1/3] net: update comments for SKB_GSO_TCP_ECN and SKB_GSO_TCP_ACCECN chia-yu.chang
2026-04-17 15:26 ` [PATCH v4 net 2/3] net: mlx5e: fix CWR handling in drivers to preserve ACE signal chia-yu.chang
2026-04-23 7:30 ` Paolo Abeni [this message]
2026-04-23 14:19 ` Dragos Tatulea
2026-04-17 15:26 ` [PATCH v4 net 3/3] net: hns3: " chia-yu.chang
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