From mboxrd@z Thu Jan 1 00:00:00 1970 From: Florian Fainelli Subject: Re: [PATCH 2/3] net: socionext: Add dummy PHY register read in phy_write() Date: Thu, 18 Oct 2018 20:01:21 -0700 Message-ID: <6b6328ad-a1a8-f3de-6618-40a703db178f@gmail.com> References: <20181019010843.3605-1-masahisa.kojima@linaro.org> <20181019010843.3605-3-masahisa.kojima@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Cc: ilias.apalodimas@linaro.org, jaswinder.singh@linaro.org, ard.biesheuvel@linaro.org, osaki.yoshitoyo@socionext.com To: masahisa.kojima@linaro.org, netdev@vger.kernel.org Return-path: Received: from mail-pf1-f196.google.com ([209.85.210.196]:46951 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726245AbeJSLFf (ORCPT ); Fri, 19 Oct 2018 07:05:35 -0400 Received: by mail-pf1-f196.google.com with SMTP id r64-v6so15797619pfb.13 for ; Thu, 18 Oct 2018 20:01:31 -0700 (PDT) In-Reply-To: <20181019010843.3605-3-masahisa.kojima@linaro.org> Content-Language: en-US Sender: netdev-owner@vger.kernel.org List-ID: On 10/18/2018 6:08 PM, masahisa.kojima@linaro.org wrote: > From: Masahisa Kojima > > There is a compatibility issue between RTL8211E implemented > in Developerbox and netsec network controller IP(F_GMAC4). > > RTL8211E expects MDC clock must be kept toggling for several > clock cycle with MDIO high before entering the IDLE state. > To meet this requirement, netsec driver needs to issue dummy > read(e.g. read PHYID1(offset 0x2) register) right after write. > > Signed-off-by: Masahisa Kojima > Signed-off-by: Yoshitoyo Osaki > --- > drivers/net/ethernet/socionext/netsec.c | 18 ++++++++++++++++-- > 1 file changed, 16 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/ethernet/socionext/netsec.c b/drivers/net/ethernet/socionext/netsec.c > index 273cc5fc07e0..e7faaf8be99e 100644 > --- a/drivers/net/ethernet/socionext/netsec.c > +++ b/drivers/net/ethernet/socionext/netsec.c > @@ -431,9 +431,12 @@ static int netsec_mac_update_to_phy_state(struct netsec_priv *priv) > return 0; > } > > +static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr); > + > static int netsec_phy_write(struct mii_bus *bus, > int phy_addr, int reg, u16 val) > { > + int status; > struct netsec_priv *priv = bus->priv; > > if (netsec_mac_write(priv, GMAC_REG_GDR, val)) > @@ -446,8 +449,19 @@ static int netsec_phy_write(struct mii_bus *bus, > GMAC_REG_SHIFT_CR_GAR))) > return -ETIMEDOUT; > > - return netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, > - NETSEC_GMAC_GAR_REG_GB); > + status = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, > + NETSEC_GMAC_GAR_REG_GB); > + > + /* Developerbox implements RTL8211E PHY and there is > + * a compatibility problem with F_GMAC4. > + * RTL8211E expects MDC clock must be kept toggling for several > + * clock cycle with MDIO high before entering the IDLE state. > + * To meet this requirement, netsec driver needs to issue dummy > + * read(e.g. read PHYID1(offset 0x2) register) right after write. > + */ > + netsec_phy_read(bus, phy_addr, 2); MII_PHYSID1 instead of 0x2 would be preferable. It is not clear to me from your commit message if this is a problem specific to your MDIO controller implementation and the RTL8211E PHY or if this is a general problem of the PHY irrespective of the MDIO controller it is interface with. If the latter, then we should seek a solution at a different layer such that other systems don't have that same problem. Thank you! -- Florian