Re: [PATCH V2 net-next 1/7] net: ena: avoid unnecessary rearming of interrupt vector when busy-polling

[Eric Dumazet <eric.dumazet@gmail.com>]

On 7/13/20 12:39 PM, Shay Agroskin wrote:
> 
> Eric Dumazet <eric.dumazet@gmail.com> writes:
> 

>>> +     WRITE_ONCE(ena_napi->interrupts_masked, true);
>>> +     smp_wmb(); /* write interrupts_masked before calling napi */
>>
>> It is not clear where is the paired smp_wmb()
>>
> Can you please explain what you mean ? The idea of adding the store barrier here is to ensure that the WRITE_ONCE(…) invocation is executed before
> invoking the napi soft irq. From what I gathered using this command would result in compiler barrier (which would prevent it from executing the bool store after napi scheduling) on x86
> and a memory barrier on ARM64 machines which have a weaker consistency model.

Every time you add a smp_wmb() somewhere, the question is raised where the opposite barrier (usually smp_rmb())
is used.

You should document this, pointing where is the opposite smp_rmb()

If you can not find it (READ_ONCE() has no implied smp_rmb()), then
something might be wrong in your patch.