From: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Manivannan Sadhasivam <mani@kernel.org>,
Richard Cochran <richardcochran@gmail.com>
Cc: mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, netdev@vger.kernel.org,
taniya.das@oss.qualcomm.com, imran.shaik@oss.qualcomm.com,
quic_vbadigan@quicinc.com, quic_mrana@quicinc.com
Subject: Re: [PATCH 4/5] bus: mhi: host: Update the Time sync logic to read 64 bit register value
Date: Wed, 8 Apr 2026 14:52:18 +0530 [thread overview]
Message-ID: <6c48fed6-27df-449b-9e43-00a68e45b9ba@oss.qualcomm.com> (raw)
In-Reply-To: <16698a59-1a2f-4816-98fe-56b125be669b@oss.qualcomm.com>
On 9/2/2025 2:44 PM, Konrad Dybcio wrote:
> On 8/18/25 8:55 AM, Krishna Chaitanya Chundru wrote:
>> Instead of reading low and high of the mhi registers twice use 64 bit
>> register value to avoid any time penality.
>>
>> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
>> ---
>> drivers/bus/mhi/host/main.c | 19 +++++++++++++++----
>> 1 file changed, 15 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/bus/mhi/host/main.c b/drivers/bus/mhi/host/main.c
>> index b7ceeb7261b708d46572d1f68dc277b6e1186b6e..f628198218ef9dc760bbfc3ec496603d1a45dfc1 100644
>> --- a/drivers/bus/mhi/host/main.c
>> +++ b/drivers/bus/mhi/host/main.c
>> @@ -1719,6 +1719,7 @@ static int mhi_get_remote_time(struct mhi_controller *mhi_cntrl, struct mhi_time
>> struct mhi_timesync_info *time)
>> {
>> struct device *dev = &mhi_cntrl->mhi_dev->dev;
>> + u64 val = U64_MAX;
>> int ret, i;
>>
>> if (!mhi_tsync && !mhi_tsync->time_reg) {
>> @@ -1756,15 +1757,25 @@ static int mhi_get_remote_time(struct mhi_controller *mhi_cntrl, struct mhi_time
>> * transition to L0.
>> */
>> for (i = 0; i < MHI_NUM_BACK_TO_BACK_READS; i++) {
>> - ret = mhi_read_reg(mhi_cntrl, mhi_tsync->time_reg,
>> - TSC_TIMESYNC_TIME_LOW_OFFSET, &time->t_dev_lo);
>> + if (mhi_cntrl->read_reg64) {
>> + ret = mhi_read_reg64(mhi_cntrl, mhi_tsync->time_reg,
>> + TSC_TIMESYNC_TIME_LOW_OFFSET, &val);
> Since you're passing mhi_cntrl to the read_reg64 function anyway,
> perhaps this could remove some verbosity:
Hi Konrad,
Sorry for late reply, in pci_generic patch we are defining read_reg64 only if
readq is defined
in the system. As per your suggesting if we go define mhi_read_reg64 always,
we need to
have #ifdef inside the mhi_read_reg64() or create a new function both of them
doesn't look
good better to have this way only.
- Krishna Chaitanya.
> int mhi_read_reg64(...) {
> u32 val_hi, val_lo;
> u64 val;
>
> if (mhi_cntrl->read_reg64) {
> ...
> } else {
> ...
> val = FIELD_PREP(GENMASK(63, 32), val_hi)) |
> FIELD_PREP(GENMASK(31, 0), val_lo));
> }
>
> return val
> }
>
>
> Konrad
next prev parent reply other threads:[~2026-04-08 9:22 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-18 6:55 [PATCH 0/5] bus: mhi: host: mhi_phc: Add support for PHC over MHI Krishna Chaitanya Chundru
2025-08-18 6:55 ` [PATCH 1/5] bus: mhi: host: Add support for non-posted TSC timesync feature Krishna Chaitanya Chundru
2025-08-18 6:55 ` [PATCH 2/5] bus: mhi: host: Add support for 64bit register reads and writes Krishna Chaitanya Chundru
2025-08-18 6:55 ` [PATCH 3/5] bus: mhi: pci_generic: Add support for 64 bit register read & write Krishna Chaitanya Chundru
2025-08-18 6:55 ` [PATCH 4/5] bus: mhi: host: Update the Time sync logic to read 64 bit register value Krishna Chaitanya Chundru
2025-09-02 9:14 ` Konrad Dybcio
2026-04-08 9:22 ` Krishna Chaitanya Chundru [this message]
2025-08-18 6:55 ` [PATCH 5/5] bus: mhi: host: mhi_phc: Add support for PHC over MHI Krishna Chaitanya Chundru
2025-08-22 1:02 ` Jakub Kicinski
2025-09-16 9:17 ` Imran Shaik
2025-10-14 10:02 ` Imran Shaik
2025-11-26 14:04 ` Manivannan Sadhasivam
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