From: Robert Hancock <hancock@sedsystems.ca>
To: Heiner Kallweit <hkallweit1@gmail.com>,
	netdev@vger.kernel.org, Florian Fainelli <f.fainelli@gmail.com>,
	Andrew Lunn <andrew@lunn.ch>
Subject: Re: [PATCH net-next v2] net: phy: xilinx: add Xilinx PHY driver
Date: Tue, 4 Jun 2019 10:39:03 -0600	[thread overview]
Message-ID: <7684776f-2bec-e9e2-1a79-dbc3e9844f7e@sedsystems.ca> (raw)
In-Reply-To: <d8c22bc3-0a20-2c24-88bb-b1f5f8cc907a@gmail.com>
On 2019-06-03 11:37 p.m., Heiner Kallweit wrote:
>> +	/* Xilinx PHY wrongly indicates BMSR_ESTATEN = 0 even though
>> +	 * extended status registers are supported. So we force the PHY
>> +	 * features to PHY_GBIT_FEATURES in order to allow gigabit support
>> +	 * to be detected.
>> +	 */
>> +	.features	= PHY_GBIT_FEATURES,
> 
> BMSR_ESTATEN is used by genphy_config_advert() too. Means you would
> need to implement your own config_aneg callback and basically
> copy 99% of genphy_config_advert().
> 
> I think the better alternative is to implement a quirk flag in phylib
> similar to PHY_RST_AFTER_CLK_EN. Let me come up with a proposal.
> 
> Last but not least: Not setting BMSR_ESTATEN for a GBit PHY violates
> the standard. Any intention from Xilinx to fix this?
My apologies, it seems like my initial diagnosis of this was incorrect.
ESTATEN is indeed set to 1. The problem is that in the configuration of
the PHY that we are using, which is set up for 1000Base-X mode, ESTATUS
returns 0x8000 indicating support for 1000Base-X full duplex and not
ESTATUS_1000_TFULL or ESTATUS_1000_THALF, which are the only bits that
genphy_config_init checks for. Therefore, genphy_config_init comes back
with no modes supported for the PHY, and phydev therefore rejects
attaching the PHY to the network device.
Adding PHY_GBIT_FEATURES in causes 1000Base-T half and full duplex to be
added into the mix, which fakes things out enough for it to work, it
appears.
So it seems like what is missing is the ability of genphy_config_init to
detect the bits in the extended status register for 1000Base-X and add
the corresponding mode flags. It appears bit 15 for 1000Base-X full
duplex is standardized in 802.3 Clause 22, so I would expect Linux
should be able to detect that and add it as a supported mode for the
PHY. genphy_config_init is dealing with the "legacy" 32-bit mode masks
that have no bit for 1000BaseX though.. how is that intended to work?
-- 
Robert Hancock
Senior Software Developer
SED Systems, a division of Calian Ltd.
Email: hancock@sedsystems.ca
next prev parent reply	other threads:[~2019-06-04 16:39 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-03 23:12 [PATCH net-next v2] net: phy: xilinx: add Xilinx PHY driver Robert Hancock
2019-06-03 23:27 ` Jesse Brandeburg
2019-06-04  2:39 ` Florian Fainelli
2019-06-04  5:37 ` Heiner Kallweit
2019-06-04 16:39   ` Robert Hancock [this message]
2019-06-04 16:54     ` Andrew Lunn
2019-06-04 17:37       ` Robert Hancock
2019-06-04 17:54       ` Heiner Kallweit
2019-06-04 18:12         ` Andrew Lunn
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