Re: [PATCH net-next v14 10/13] net: mdio: realtek-rtl9300: Open up C22 and C45 space in parallel

[Andrew Lunn <andrew@lunn.ch>]

On Tue, Aug 18, 2026 at 07:44:58PM +0200, Markus Stockhausen wrote:
> > Von: Andrew Lunn <andrew@lunn.ch> 
> > Gesendet: Montag, 17. August 2026 22:32
> > An: Markus Stockhausen <markus.stockhausen@gmx.de>
> > Betreff: Re: [PATCH net-next v14 10/13] net: mdio: realtek-rtl9300: Open
> up C22 and C45 space in parallel
> > ...
> > > Until now we never encountered any of these PHYs in scope 
> > > (RTL8218x octa port) outside of the Realtek RTL83xx/RTL93xx 
> > > ecosystem.
> > 
> > Is the ID in registers 2 and 2 specific to the RTL83xx/RTL93xx ?  That
> > would make thinks simple.
> 
> There is no difference in the ID registers of the RTL8218 that
> is attached to RTL83xx/RTL93xx or to possible other SOCs.
> The RTL8218 series has a lot in common with the lower port
> designs (e.g. RTL8211). They are driven by dual QSGMII and
> can be attached to any non Realtek SOC.
> 
> If upstream rtlgen_read_mmd() is not the proper way then
> I must think about it. But that needs to wait a bit ...

I _think_ this becomes an issue when you have working C45 over C22,
but no C45. I can think of two solutions:

1. rtlgen_read_mmd() pokes around in the bus to find out if C45 is
supported, and if not, do C45 over C22.

2. When dealing with this horribly broken hardware polling, you trap
read/writes to C45 over C22 and emulate them using C45. That at least
keeps the workaround where it belongs, in the broken MDIO bus driver,
rather than the PHY driver.

	Andrew