From: "Cheatham, Benjamin" <benjamin.cheatham@amd.com>
To: <alejandro.lucero-palau@amd.com>
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
<linux-cxl@vger.kernel.org>, <netdev@vger.kernel.org>,
<dan.j.williams@intel.com>, <edward.cree@amd.com>,
<davem@davemloft.net>, <kuba@kernel.org>, <pabeni@redhat.com>,
<edumazet@google.com>, <dave.jiang@intel.com>
Subject: Re: [PATCH v19 11/22] cxl: Define a driver interface for HPA free space enumeration
Date: Thu, 9 Oct 2025 15:55:51 -0500 [thread overview]
Message-ID: <7a3d3249-ee08-4fe0-a016-829ece6f7b8e@amd.com> (raw)
In-Reply-To: <20251006100130.2623388-12-alejandro.lucero-palau@amd.com>
On 10/6/2025 5:01 AM, alejandro.lucero-palau@amd.com wrote:
> From: Alejandro Lucero <alucerop@amd.com>
>
> CXL region creation involves allocating capacity from Device Physical Address
> (DPA) and assigning it to decode a given Host Physical Address (HPA). Before
> determining how much DPA to allocate the amount of available HPA must be
> determined. Also, not all HPA is created equal, some HPA targets RAM, some
> targets PMEM, some is prepared for device-memory flows like HDM-D and HDM-DB,
> and some is HDM-H (host-only).
>
> In order to support Type2 CXL devices, wrap all of those concerns into
> an API that retrieves a root decoder (platform CXL window) that fits the
> specified constraints and the capacity available for a new region.
>
> Add a complementary function for releasing the reference to such root
> decoder.
>
> Based on https://lore.kernel.org/linux-cxl/168592159290.1948938.13522227102445462976.stgit@dwillia2-xfh.jf.intel.com/
>
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
Hey Alejandro,
I've been testing this on my setup and noticed a few issues when BIOS sets up the HDM decoders. It came down to 2 issues:
1) Enabling "Specific Purpose Memory" added a Soft Reserve resource below the CXL window resource and broke
this patch (more below)
2) The endpoint decoder was already set up which broke DPA allocation and then CXL region creation (see my response
to patch 18/22 for fix and explanation)
The fix I did for 1 is a bit hacky but it's essentially checking none of the resources below the CXL window are onlined as
system memory. It's roughly equivalent to what's being done in the CXL_PARTMODE_RAM case of cxl_region_probe(), but
I'm restricting the resources to "Soft Reserved" to be safe.
The diff for 2 is pretty big. If you don't want to take it at this point I can send it as a follow up. In that case I'd definitely
add that auto regions won't work in at least the cover letter (and in the description of 18/22 as well?).
---
diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index acaca64764bf..2d60131edff3 100644
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -784,6 +784,19 @@ static int find_max_hpa(struct device *dev, void *data)
lockdep_assert_held_read(&cxl_rwsem.region);
res = cxlrd->res->child;
+ /*
+ * BIOS may have marked the CXL window as soft reserved. Make sure it's
+ * free to use.
+ */
+ while (res && resource_size(res) == resource_size(cxlrd->res)) {
+ if ((res->flags & IORESOURCE_BUSY) ||
+ (res->flags & IORESOURCE_SYSRAM) ||
+ strcmp(res->name, "Soft Reserved") != 0)
+ return 0;
+
+ res = res->child;
+ }
+
/* With no resource child the whole parent resource is available */
if (!res)
max = resource_size(cxlrd->res);
next prev parent reply other threads:[~2025-10-09 20:56 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-06 10:01 [PATCH v19 00/22] Type2 device basic support alejandro.lucero-palau
2025-10-06 10:01 ` [PATCH v19 01/22] cxl/mem: Arrange for always-synchronous memdev attach alejandro.lucero-palau
2025-10-07 12:40 ` Jonathan Cameron
2025-10-07 12:42 ` Jonathan Cameron
2025-10-10 23:11 ` Dave Jiang
2025-10-29 11:20 ` Alejandro Lucero Palau
2025-10-30 19:57 ` Koralahalli Channabasappa, Smita
2025-11-10 10:43 ` Alejandro Lucero Palau
2025-10-06 10:01 ` [PATCH v19 02/22] cxl/port: Arrange for always synchronous endpoint attach alejandro.lucero-palau
2025-10-06 10:01 ` [PATCH v19 03/22] cxl/mem: Introduce a memdev creation ->probe() operation alejandro.lucero-palau
2025-10-06 10:01 ` [PATCH v19 04/22] cxl: Add type2 device basic support alejandro.lucero-palau
2025-10-06 10:01 ` [PATCH v19 05/22] sfc: add cxl support alejandro.lucero-palau
2025-10-06 10:01 ` [PATCH v19 06/22] cxl: Move pci generic code alejandro.lucero-palau
2025-10-07 13:01 ` Jonathan Cameron
2025-11-10 11:23 ` Alejandro Lucero Palau
2025-11-11 13:41 ` Jonathan Cameron
2025-10-06 10:01 ` [PATCH v19 07/22] cxl: allow Type2 drivers to map cxl component regs alejandro.lucero-palau
2025-10-07 13:18 ` Jonathan Cameron
2025-11-10 11:28 ` Alejandro Lucero Palau
2025-10-06 10:01 ` [PATCH v19 08/22] cxl: Support dpa initialization without a mailbox alejandro.lucero-palau
2025-10-07 13:22 ` Jonathan Cameron
2025-11-10 11:28 ` Alejandro Lucero Palau
2025-10-06 10:01 ` [PATCH v19 09/22] cxl: Prepare memdev creation for type2 alejandro.lucero-palau
2025-10-06 10:01 ` [PATCH v19 10/22] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-10-06 10:01 ` [PATCH v19 11/22] cxl: Define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-10-07 13:43 ` Jonathan Cameron
2025-11-10 11:46 ` Alejandro Lucero Palau
2025-10-09 20:55 ` Cheatham, Benjamin [this message]
2025-10-10 11:16 ` Alejandro Lucero Palau
2025-10-15 17:52 ` Dave Jiang
2025-10-15 18:17 ` Dave Jiang
2025-11-10 11:57 ` Alejandro Lucero Palau
2025-10-06 10:01 ` [PATCH v19 12/22] sfc: get root decoder alejandro.lucero-palau
2025-10-06 10:01 ` [PATCH v19 13/22] cxl: Define a driver interface for DPA allocation alejandro.lucero-palau
2025-10-07 13:52 ` Jonathan Cameron
2025-10-15 20:07 ` Dave Jiang
2025-11-10 12:02 ` Alejandro Lucero Palau
2025-10-15 20:08 ` Dave Jiang
2025-11-10 12:04 ` Alejandro Lucero Palau
2025-10-06 10:01 ` [PATCH v19 14/22] sfc: get endpoint decoder alejandro.lucero-palau
2025-10-15 20:15 ` Dave Jiang
2025-11-10 12:08 ` Alejandro Lucero Palau
2025-10-06 10:01 ` [PATCH v19 15/22] cxl: Make region type based on endpoint type alejandro.lucero-palau
2025-10-06 10:01 ` [PATCH v19 16/22] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2025-10-06 10:01 ` [PATCH v19 17/22] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2025-10-06 10:01 ` [PATCH v19 18/22] cxl: Allow region creation by type2 drivers alejandro.lucero-palau
2025-10-07 14:11 ` Jonathan Cameron
2025-11-10 13:47 ` Alejandro Lucero Palau
2025-11-11 14:04 ` Jonathan Cameron
2025-10-09 20:56 ` Cheatham, Benjamin
2025-10-15 21:42 ` Dave Jiang
2025-10-16 13:23 ` Cheatham, Benjamin
2025-10-20 13:24 ` Alejandro Lucero Palau
2025-10-20 13:59 ` Dave Jiang
2025-10-20 14:59 ` Alejandro Lucero Palau
2025-10-15 21:36 ` Dave Jiang
2025-10-20 13:04 ` Alejandro Lucero Palau
2025-10-06 10:01 ` [PATCH v19 19/22] cxl: Avoid dax creation for accelerators alejandro.lucero-palau
2025-10-06 10:01 ` [PATCH v19 20/22] sfc: create cxl region alejandro.lucero-palau
2025-10-07 14:13 ` Jonathan Cameron
2025-10-06 10:01 ` [PATCH v19 21/22] cxl: Add function for obtaining region range alejandro.lucero-palau
2025-10-06 10:01 ` [PATCH v19 22/22] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-10-07 14:48 ` Jonathan Cameron
2025-11-10 14:54 ` Alejandro Lucero Palau
2025-10-07 23:41 ` [PATCH v19 00/22] Type2 device basic support Dave Jiang
2025-10-10 10:39 ` Alejandro Lucero Palau
2025-10-10 15:57 ` Dave Jiang
2025-10-10 16:54 ` Dave Jiang
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