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[2a02:3100:af43:5200:e57d:90a4:e6b5:1175]) by smtp.googlemail.com with ESMTPSA id a640c23a62f3a-abf0c0b99bcsm360391766b.24.2025.02.28.14.57.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 28 Feb 2025 14:57:24 -0800 (PST) Message-ID: <7b32aa88-d3bc-4414-a124-59befc3dc098@gmail.com> Date: Fri, 28 Feb 2025 23:58:27 +0100 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next 2/3] r8169: enable RTL8168H/RTL8168EP/RTL8168FP/RTL8125/RTL8126 LTR support To: Bjorn Helgaas , Hau Cc: nic_swsd , "andrew+netdev@lunn.ch" , "davem@davemloft.net" , "edumazet@google.com" , "kuba@kernel.org" , "pabeni@redhat.com" , Bjorn Helgaas , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pci@vger.kernel.org" References: <20250224190013.GA469168@bhelgaas> Content-Language: en-US From: Heiner Kallweit Autocrypt: addr=hkallweit1@gmail.com; keydata= xsFNBF/0ZFUBEAC0eZyktSE7ZNO1SFXL6cQ4i4g6Ah3mOUIXSB4pCY5kQ6OLKHh0FlOD5/5/ sY7IoIouzOjyFdFPnz4Bl3927ClT567hUJJ+SNaFEiJ9vadI6vZm2gcY4ExdIevYHWe1msJF MVE4yNwdS+UsPeCF/6CQQTzHc+n7DomE7fjJD5J1hOJjqz2XWe71fTvYXzxCFLwXXbBiqDC9 dNqOe5odPsa4TsWZ09T33g5n2nzTJs4Zw8fCy8rLqix/raVsqr8fw5qM66MVtdmEljFaJ9N8 /W56qGCp+H8Igk/F7CjlbWXiOlKHA25mPTmbVp7VlFsvsmMokr/imQr+0nXtmvYVaKEUwY2g 86IU6RAOuA8E0J5bD/BeyZdMyVEtX1kT404UJZekFytJZrDZetwxM/cAH+1fMx4z751WJmxQ J7mIXSPuDfeJhRDt9sGM6aRVfXbZt+wBogxyXepmnlv9K4A13z9DVLdKLrYUiu9/5QEl6fgI kPaXlAZmJsQfoKbmPqCHVRYj1lpQtDM/2/BO6gHASflWUHzwmBVZbS/XRs64uJO8CB3+V3fa cIivllReueGCMsHh6/8wgPAyopXOWOxbLsZ291fmZqIR0L5Y6b2HvdFN1Xhc+YrQ8TKK+Z4R mJRDh0wNQ8Gm89g92/YkHji4jIWlp2fwzCcx5+lZCQ1XdqAiHQARAQABzSZIZWluZXIgS2Fs bHdlaXQgPGhrYWxsd2VpdDFAZ21haWwuY29tPsLBjgQTAQgAOBYhBGxfqY/yOyXjyjJehXLe ig9U8DoMBQJf9GRVAhsDBQsJCAcCBhUKCQgLAgQWAgMBAh4BAheAAAoJEHLeig9U8DoMSycQ AJbfg8HZEK0ljV4M8nvdaiNixWAufrcZ+SD8zhbxl8GispK4F3Yo+20Y3UoZ7FcIidJWUUJL axAOkpI/70YNhlqAPMsuudlAieeYZKjIv1WV5ucNZ3VJ7dC+dlVqQdAr1iD869FZXvy91KhJ wYulyCf+s4T9YgmLC6jLMBZghKIf1uhSd0NzjyCqYWbk2ZxByZHgunEShOhHPHswu3Am0ftt ePaYIHgZs+Vzwfjs8I7EuW/5/f5G9w1vibXxtGY/GXwgGGHRDjFM7RSprGOv4F5eMGh+NFUJ TU9N96PQYMwXVxnQfRXl8O6ffSVmFx4H9rovxWPKobLmqQL0WKLLVvA/aOHCcMKgfyKRcLah 57vGC50Ga8oT2K1g0AhKGkyJo7lGXkMu5yEs0m9O+btqAB261/E3DRxfI1P/tvDZpLJKtq35 dXsj6sjvhgX7VxXhY1wE54uqLLHY3UZQlmH3QF5t80MS7/KhxB1pO1Cpcmkt9hgyzH8+5org +9wWxGUtJWNP7CppY+qvv3SZtKJMKsxqk5coBGwNkMms56z4qfJm2PUtJQGjA65XWdzQACib 2iaDQoBqGZfXRdPT0tC1H5kUJuOX4ll1hI/HBMEFCcO8++Bl2wcrUsAxLzGvhINVJX2DAQaF aNetToazkCnzubKfBOyiTqFJ0b63c5dqziAgzsFNBF/0ZFUBEADF8UEZmKDl1w/UxvjeyAeX kghYkY3bkK6gcIYXdLRfJw12GbvMioSguvVzASVHG8h7NbNjk1yur6AONfbUpXKSNZ0skV8V fG+ppbaY+zQofsSMoj5gP0amwbwvPzVqZCYJai81VobefTX2MZM2Mg/ThBVtGyzV3NeCpnBa 8AX3s9rrX2XUoCibYotbbxx9afZYUFyflOc7kEpc9uJXIdaxS2Z6MnYLHsyVjiU6tzKCiVOU KJevqvzPXJmy0xaOVf7mhFSNQyJTrZpLa+tvB1DQRS08CqYtIMxRrVtC0t0LFeQGly6bOngr ircurWJiJKbSXVstLHgWYiq3/GmCSx/82ObeLO3PftklpRj8d+kFbrvrqBgjWtMH4WtK5uN5 1WJ71hWJfNchKRlaJ3GWy8KolCAoGsQMovn/ZEXxrGs1ndafu47yXOpuDAozoHTBGvuSXSZo ythk/0EAuz5IkwkhYBT1MGIAvNSn9ivE5aRnBazugy0rTRkVggHvt3/7flFHlGVGpBHxFUwb /a4UjJBPtIwa4tWR8B1Ma36S8Jk456k2n1id7M0LQ+eqstmp6Y+UB+pt9NX6t0Slw1NCdYTW gJezWTVKF7pmTdXszXGxlc9kTrVUz04PqPjnYbv5UWuDd2eyzGjrrFOsJEi8OK2d2j4FfF++ AzOMdW09JVqejQARAQABwsF2BBgBCAAgFiEEbF+pj/I7JePKMl6Fct6KD1TwOgwFAl/0ZFUC GwwACgkQct6KD1TwOgxUfg//eAoYc0Vm4NrxymfcY30UjHVD0LgSvU8kUmXxil3qhFPS7KA+ y7tgcKLHOkZkXMX5MLFcS9+SmrAjSBBV8omKoHNo+kfFx/dUAtz0lot8wNGmWb+NcHeKM1eb nwUMOEa1uDdfZeKef/U/2uHBceY7Gc6zPZPWgXghEyQMTH2UhLgeam8yglyO+A6RXCh+s6ak Wje7Vo1wGK4eYxp6pwMPJXLMsI0ii/2k3YPEJPv+yJf90MbYyQSbkTwZhrsokjQEaIfjrIk3 rQRjTve/J62WIO28IbY/mENuGgWehRlTAbhC4BLTZ5uYS0YMQCR7v9UGMWdNWXFyrOB6PjSu Trn9MsPoUc8qI72mVpxEXQDLlrd2ijEWm7Nrf52YMD7hL6rXXuis7R6zY8WnnBhW0uCfhajx q+KuARXC0sDLztcjaS3ayXonpoCPZep2Bd5xqE4Ln8/COCslP7E92W1uf1EcdXXIrx1acg21 H/0Z53okMykVs3a8tECPHIxnre2UxKdTbCEkjkR4V6JyplTS47oWMw3zyI7zkaadfzVFBxk2 lo/Tny+FX1Azea3Ce7oOnRUEZtWSsUidtIjmL8YUQFZYm+JUIgfRmSpMFq8JP4VH43GXpB/S OCrl+/xujzvoUBFV/cHKjEQYBxo+MaiQa1U54ykM2W4DnHb1UiEf5xDkFd4= In-Reply-To: <20250224190013.GA469168@bhelgaas> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 24.02.2025 20:00, Bjorn Helgaas wrote: > On Mon, Feb 24, 2025 at 04:33:50PM +0000, Hau wrote: >>> On 21.02.2025 08:18, ChunHao Lin wrote: >>>> This patch will enable RTL8168H/RTL8168EP/RTL8168FP/RTL8125/RTL8126 >>>> LTR support on the platforms that have tested with LTR enabled. >>> >>> Where in the code is the check whether platform has been tested with LTR? >>> >> LTR is for L1,2. But L1 will be disabled when rtl_aspm_is_safe() >> return false. So LTR needs rtl_aspm_is_safe() to return true. >> >>>> Signed-off-by: ChunHao Lin >>>> --- >>>> drivers/net/ethernet/realtek/r8169_main.c | 108 >>>> ++++++++++++++++++++++ >>>> 1 file changed, 108 insertions(+) >>>> >>>> diff --git a/drivers/net/ethernet/realtek/r8169_main.c >>>> b/drivers/net/ethernet/realtek/r8169_main.c >>>> index 731302361989..9953eaa01c9d 100644 >>>> --- a/drivers/net/ethernet/realtek/r8169_main.c >>>> +++ b/drivers/net/ethernet/realtek/r8169_main.c >>>> @@ -2955,6 +2955,111 @@ static void rtl_disable_exit_l1(struct >>> rtl8169_private *tp) >>>> } >>>> } >>>> >>>> +static void rtl_set_ltr_latency(struct rtl8169_private *tp) { >>>> + switch (tp->mac_version) { >>>> + case RTL_GIGA_MAC_VER_70: >>>> + case RTL_GIGA_MAC_VER_71: >>>> + r8168_mac_ocp_write(tp, 0xcdd0, 0x9003); >>>> + r8168_mac_ocp_write(tp, 0xcdd2, 0x8c09); >>>> + r8168_mac_ocp_write(tp, 0xcdd8, 0x9003); >>>> + r8168_mac_ocp_write(tp, 0xcdd4, 0x9003); >>>> + r8168_mac_ocp_write(tp, 0xcdda, 0x9003); >>>> + r8168_mac_ocp_write(tp, 0xcdd6, 0x9003); >>>> + r8168_mac_ocp_write(tp, 0xcddc, 0x9003); >>>> + r8168_mac_ocp_write(tp, 0xcde8, 0x887a); >>>> + r8168_mac_ocp_write(tp, 0xcdea, 0x9003); >>>> + r8168_mac_ocp_write(tp, 0xcdec, 0x8c09); >>>> + r8168_mac_ocp_write(tp, 0xcdee, 0x9003); >>>> + r8168_mac_ocp_write(tp, 0xcdf0, 0x8a62); >>>> + r8168_mac_ocp_write(tp, 0xcdf2, 0x9003); >>>> + r8168_mac_ocp_write(tp, 0xcdf4, 0x883e); >>>> + r8168_mac_ocp_write(tp, 0xcdf6, 0x9003); >>>> + break; >>>> + case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: >>>> + r8168_mac_ocp_write(tp, 0xcdd0, 0x9003); >>>> + r8168_mac_ocp_write(tp, 0xcdd2, 0x889c); >>>> + r8168_mac_ocp_write(tp, 0xcdd8, 0x9003); >>>> + r8168_mac_ocp_write(tp, 0xcdd4, 0x8c30); >>>> + r8168_mac_ocp_write(tp, 0xcdda, 0x9003); >>>> + r8168_mac_ocp_write(tp, 0xcdd6, 0x9003); >>>> + r8168_mac_ocp_write(tp, 0xcddc, 0x9003); >>>> + r8168_mac_ocp_write(tp, 0xcde8, 0x883e); >>>> + r8168_mac_ocp_write(tp, 0xcdea, 0x9003); >>>> + r8168_mac_ocp_write(tp, 0xcdec, 0x889c); >>>> + r8168_mac_ocp_write(tp, 0xcdee, 0x9003); >>>> + r8168_mac_ocp_write(tp, 0xcdf0, 0x8C09); >>>> + r8168_mac_ocp_write(tp, 0xcdf2, 0x9003); >>>> + break; >>>> + case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_53: >>>> + r8168_mac_ocp_write(tp, 0xcdd8, 0x9003); >>>> + r8168_mac_ocp_write(tp, 0xcdda, 0x9003); >>>> + r8168_mac_ocp_write(tp, 0xcddc, 0x9003); >>>> + r8168_mac_ocp_write(tp, 0xcdd2, 0x883c); >>>> + r8168_mac_ocp_write(tp, 0xcdd4, 0x8c12); >>>> + r8168_mac_ocp_write(tp, 0xcdd6, 0x9003); >>>> + break; >>>> + default: >>>> + break; >>>> + } >>>> +} >>>> + >>>> +static void rtl_reset_pci_ltr(struct rtl8169_private *tp) { >>>> + struct pci_dev *pdev = tp->pci_dev; >>>> + u16 cap; >>>> + >>>> + pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap); >>>> + if (cap & PCI_EXP_DEVCTL2_LTR_EN) { >>>> + pcie_capability_clear_word(pdev, PCI_EXP_DEVCTL2, >>>> + PCI_EXP_DEVCTL2_LTR_EN); >>>> + pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2, >>>> + PCI_EXP_DEVCTL2_LTR_EN); >>> >>> I'd prefer that only PCI core deals with these registers >>> (functions like pci_configure_ltr()). Any specific reason for this >>> reset? Is it something which could be applicable for other devices >>> too, so that the PCI core should be extended? >>> >> It is for specific platform. On that platform driver needs to do >> this to let LTR works. > I interpret this in a way that the chip triggers some internal LTR configuration activity if it detects bit PCI_EXP_DEVCTL2_LTR_EN changing from 0 to 1. And this needed activity isn't triggered if PCI_EXP_DEVCTL2_LTR_EN is set already and doesn't change. Hau, is this correct? So the PCI_EXP_DEVCTL2_LTR_EN reset is some kind of needed quirk. However PCI quirks are applied too early, before we even detected the chip version in probe(). Therefore I also think a helper for this reset in PCI core would be best. And what hasn't been mentioned yet: We have to skip the chip-specific LTR configuration if pci_dev->ltr_path isn't set. > This definitely looks like code that should not be in a driver. > Drivers shouldn't need to touch ASPM or LTR configuration unless > there's a device defect to work around, and that should use a PCI core > interface. Depending on what the defect is, we may need to add a new > interface. > > This clear/set of PCI_EXP_DEVCTL2_LTR_EN when it was already set could > work around some kind of device defect, or it could be a hint that > something in the PCI core is broken. Maybe the core is configuring > ASPM/LTR incorrectly. > > Bjorn