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From: "Cheatham, Benjamin" <benjamin.cheatham@amd.com>
To: Alejandro Lucero Palau <alucerop@amd.com>,
	<alejandro.lucero-palau@amd.com>
Cc: Zhi Wang <zhiw@nvidia.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Alison Schofield <alison.schofield@intel.com>,
	<linux-cxl@vger.kernel.org>, <netdev@vger.kernel.org>,
	<dan.j.williams@intel.com>, <edward.cree@amd.com>,
	<davem@davemloft.net>, <kuba@kernel.org>, <pabeni@redhat.com>,
	<edumazet@google.com>, <dave.jiang@intel.com>
Subject: Re: [PATCH v23 17/22] cxl/region: Factor out interleave ways setup
Date: Thu, 19 Feb 2026 11:29:04 -0600	[thread overview]
Message-ID: <80cbdf15-24d2-4b37-aafb-b26c22feb53a@amd.com> (raw)
In-Reply-To: <62be78b6-1d5d-4b5f-aaf7-62996536c97d@amd.com>



On 2/19/2026 4:40 AM, Alejandro Lucero Palau wrote:
> 
> On 2/11/26 22:11, Cheatham, Benjamin wrote:
>> On 2/1/2026 9:54 AM, alejandro.lucero-palau@amd.com wrote:
>>> From: Alejandro Lucero <alucerop@amd.com>
>>>
>>> Region creation based on Type3 devices is triggered from user space
>>> allowing memory combination through interleaving.
>>>
>>> In preparation for kernel driven region creation, that is Type2 drivers
>>> triggering region creation backed with its advertised CXL memory, factor
>>> out a common helper from the user-sysfs region setup for interleave ways.
>>>
>>> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
>>> Reviewed-by: Zhi Wang <zhiw@nvidia.com>
>>> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
>>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>>> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
>>> Reviewed-by: Alison Schofield <alison.schofield@intel.com>
>>> ---
>>>   drivers/cxl/core/region.c | 43 ++++++++++++++++++++++++---------------
>>>   1 file changed, 27 insertions(+), 16 deletions(-)
>>>
>>> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
>>> index f53b2e9fd9e6..ece1d3df7cf1 100644
>>> --- a/drivers/cxl/core/region.c
>>> +++ b/drivers/cxl/core/region.c
>>> @@ -485,22 +485,14 @@ static ssize_t interleave_ways_show(struct device *dev,
>>>     static const struct attribute_group *get_cxl_region_target_group(void);
>>>   -static ssize_t interleave_ways_store(struct device *dev,
>>> -                     struct device_attribute *attr,
>>> -                     const char *buf, size_t len)
>>> +static int set_interleave_ways(struct cxl_region *cxlr, int val)
>> @val should probably stay an unsigned int. You pass an unsigned int in the sysfs function, and the
>> function was originally coded with that in mind (same with @save below).
> 
> Good catch. I wonder if I should just change the way the value is obtained, using kstrtoint instead  of kstrtouint, as those values are used for cxl_region_params fields defined as int. In other words, it seems doing that simpler than changing all the other places you mention and the structs involved. I can not see a reason for using unsigned int so I think I will follow that approach. Tell me if you think otherwise.
> 

If I had to guess unsigned int was used because a negative interleave granularity/ways makes no sense. I think your suggestion is fine though since no one
in their right mind would give anything but a (relatively) small and positive value for these.

Thanks,
Ben

> 
> Thank you
> 
> 
>> With that cleaned up:
>> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
>>
>>>   {
>>> -    struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev->parent);
>>> +    struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent);
>>>       struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
>>> -    struct cxl_region *cxlr = to_cxl_region(dev);
>>>       struct cxl_region_params *p = &cxlr->params;
>>> -    unsigned int val, save;
>>> -    int rc;
>>> +    int save, rc;
>>>       u8 iw;
>>>   -    rc = kstrtouint(buf, 0, &val);
>>> -    if (rc)
>>> -        return rc;
>>> -
>>>       rc = ways_to_eiw(val, &iw);
>>>       if (rc)
>>>           return rc;
>>> @@ -515,9 +507,7 @@ static ssize_t interleave_ways_store(struct device *dev,
>>>           return -EINVAL;
>>>       }
>>>   -    ACQUIRE(rwsem_write_kill, rwsem)(&cxl_rwsem.region);
>>> -    if ((rc = ACQUIRE_ERR(rwsem_write_kill, &rwsem)))
>>> -        return rc;
>>> +    lockdep_assert_held_write(&cxl_rwsem.region);
>>>         if (p->state >= CXL_CONFIG_INTERLEAVE_ACTIVE)
>>>           return -EBUSY;
>>> @@ -525,10 +515,31 @@ static ssize_t interleave_ways_store(struct device *dev,
>>>       save = p->interleave_ways;
>>>       p->interleave_ways = val;
>>>       rc = sysfs_update_group(&cxlr->dev.kobj, get_cxl_region_target_group());
>>> -    if (rc) {
>>> +    if (rc)
>>>           p->interleave_ways = save;
>>> +
>>> +    return rc;
>>> +}
>>> +
>>> +static ssize_t interleave_ways_store(struct device *dev,
>>> +                     struct device_attribute *attr,
>>> +                     const char *buf, size_t len)
>>> +{
>>> +    struct cxl_region *cxlr = to_cxl_region(dev);
>>> +    unsigned int val;
>>> +    int rc;
>>> +
>>> +    rc = kstrtouint(buf, 0, &val);
>>> +    if (rc)
>>> +        return rc;
>>> +
>>> +    ACQUIRE(rwsem_write_kill, rwsem)(&cxl_rwsem.region);
>>> +    if ((rc = ACQUIRE_ERR(rwsem_write_kill, &rwsem)))
>>> +        return rc;
>>> +
>>> +    rc = set_interleave_ways(cxlr, val);
>>> +    if (rc)
>>>           return rc;
>>> -    }
>>>         return len;
>>>   }


  reply	other threads:[~2026-02-19 17:29 UTC|newest]

Thread overview: 67+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-01 15:54 [PATCH v23 00/22] Type2 device basic support alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 01/22] cxl: Add type2 " alejandro.lucero-palau
2026-02-11 22:11   ` Cheatham, Benjamin
2026-02-19  8:52     ` Alejandro Lucero Palau
2026-02-01 15:54 ` [PATCH v23 02/22] sfc: add cxl support alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 03/22] cxl: Move pci generic code alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 04/22] cxl/sfc: Map cxl component regs alejandro.lucero-palau
2026-03-20 17:22   ` Edward Cree
2026-02-01 15:54 ` [PATCH v23 05/22] cxl/sfc: Initialize dpa without a mailbox alejandro.lucero-palau
2026-03-20 17:24   ` Edward Cree
2026-02-01 15:54 ` [PATCH v23 06/22] cxl: Prepare memdev creation for type2 alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 07/22] sfc: create type2 cxl memdev alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 08/22] cxl/hdm: Add support for getting region from committed decoder alejandro.lucero-palau
2026-02-11 22:11   ` Cheatham, Benjamin
2026-02-12  9:16     ` Alejandro Lucero Palau
2026-03-09 22:49       ` PJ Waskiewicz
2026-03-10 13:54         ` Alejandro Lucero Palau
2026-03-13  2:03         ` Dan Williams
2026-03-13 13:10           ` Alejandro Lucero Palau
2026-03-16 14:33             ` Alejandro Lucero Palau
2026-02-01 15:54 ` [PATCH v23 09/22] cxl: Add function for obtaining region range alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 10/22] cxl: Export function for unwinding cxl by accelerators alejandro.lucero-palau
2026-02-19 23:16   ` Dave Jiang
2026-02-21  4:48   ` Gregory Price
2026-02-01 15:54 ` [PATCH v23 11/22] sfc: obtain decoder and region if committed by firmware alejandro.lucero-palau
2026-02-11 22:10   ` Cheatham, Benjamin
2026-02-19  8:55     ` Alejandro Lucero Palau
2026-02-19 23:31   ` Dave Jiang
2026-02-20  8:08     ` Alejandro Lucero Palau
2026-03-20 17:25   ` Edward Cree
2026-02-01 15:54 ` [PATCH v23 12/22] cxl: Define a driver interface for HPA free space enumeration alejandro.lucero-palau
2026-02-11 22:10   ` Cheatham, Benjamin
2026-02-19  9:58     ` Alejandro Lucero Palau
2026-02-19 17:29       ` Cheatham, Benjamin
2026-02-20 15:42   ` Dave Jiang
2026-02-26 16:13   ` Alejandro Lucero Palau
2026-02-01 15:54 ` [PATCH v23 13/22] sfc: get root decoder alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 14/22] cxl: Define a driver interface for DPA allocation alejandro.lucero-palau
2026-02-11 22:10   ` Cheatham, Benjamin
2026-02-11 22:12   ` Cheatham, Benjamin
2026-02-19 10:26     ` Alejandro Lucero Palau
2026-02-13 16:14   ` [PATCH " Gregory Price
2026-02-16 12:34     ` Alejandro Lucero Palau
2026-02-01 15:54 ` [PATCH v23 15/22] sfc: get endpoint decoder alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 16/22] cxl: Make region type based on endpoint type alejandro.lucero-palau
2026-02-11 22:11   ` Cheatham, Benjamin
2026-02-01 15:54 ` [PATCH v23 17/22] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2026-02-11 22:11   ` Cheatham, Benjamin
2026-02-19 10:40     ` Alejandro Lucero Palau
2026-02-19 17:29       ` Cheatham, Benjamin [this message]
2026-02-01 15:54 ` [PATCH v23 18/22] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2026-02-11 22:11   ` Cheatham, Benjamin
2026-02-01 15:54 ` [PATCH v23 19/22] cxl: Allow region creation by type2 drivers alejandro.lucero-palau
2026-02-11 22:11   ` Cheatham, Benjamin
2026-02-19 10:48     ` Alejandro Lucero Palau
2026-02-01 15:54 ` [PATCH v23 20/22] cxl: Avoid dax creation for accelerators alejandro.lucero-palau
2026-02-11 22:10   ` Cheatham, Benjamin
2026-02-19 10:50     ` Alejandro Lucero Palau
2026-02-01 15:54 ` [PATCH v23 21/22] sfc: create cxl region alejandro.lucero-palau
2026-02-13 16:14   ` [PATCH " Gregory Price
2026-02-20  8:00     ` Alejandro Lucero Palau
2026-02-01 15:54 ` [PATCH v23 22/22] sfc: support pio mapping based on cxl alejandro.lucero-palau
2026-02-13 16:14   ` [PATCH " Gregory Price
2026-02-20  8:04     ` Alejandro Lucero Palau
2026-02-11 22:12 ` [PATCH v23 00/22] Type2 device basic support Cheatham, Benjamin
2026-03-09 22:43 ` PJ Waskiewicz
2026-03-10 14:02   ` Alejandro Lucero Palau

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