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From: Avigail Dahan <Avigailx.dahan@intel.com>
To: Chwee-Lin Choong <chwee.lin.choong@intel.com>,
	Tony Nguyen <anthony.l.nguyen@intel.com>,
	Przemek Kitszel <przemyslaw.kitszel@intel.com>,
	Andrew Lunn <andrew+netdev@lunn.ch>,
	"David S . Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Richard Cochran <richardcochran@gmail.com>,
	Vinicius Costa Gomes <vinicius.gomes@intel.com>
Cc: <yipeng.chai@amd.com>, <alexander.deucher@amd.com>,
	<intel-wired-lan@lists.osuosl.org>, <netdev@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	Aleksandr Loktionov <aleksandr.loktionov@intel.com>,
	Avi Shalev <avi.shalev@intel.com>,
	"Song Yoong Siang" <yoong.siang.song@intel.com>
Subject: Re: [Intel-wired-lan] [PATCH iwl-net v4] igc: fix race condition in TX timestamp read for register 0
Date: Mon, 29 Dec 2025 16:52:36 +0200	[thread overview]
Message-ID: <8338c85b-28c0-47f7-8e80-5448d7490f33@intel.com> (raw)
In-Reply-To: <20251128105304.8147-1-chwee.lin.choong@intel.com>



On 28/11/2025 12:53, Chwee-Lin Choong wrote:
> The current HW bug workaround checks the TXTT_0 ready bit first,
> then reads TXSTMPL_0 twice (before and after reading TXSTMPH_0)
> to detect whether a new timestamp was captured by timestamp
> register 0 during the workaround.
> 
> This sequence has a race: if a new timestamp is captured after
> checking the TXTT_0 bit but before the first TXSTMPL_0 read, the
> detection fails because both the “old” and “new” values come from
> the same timestamp.
> 
> Fix by reading TXSTMPL_0 first to establish a baseline, then
> checking the TXTT_0 bit. This ensures any timestamp captured
> during the race window will be detected.
> 
> Old sequence:
>    1. Check TXTT_0 ready bit
>    2. Read TXSTMPL_0 (baseline)
>    3. Read TXSTMPH_0 (interrupt workaround)
>    4. Read TXSTMPL_0 (detect changes vs baseline)
> 
> New sequence:
>    1. Read TXSTMPL_0 (baseline)
>    2. Check TXTT_0 ready bit
>    3. Read TXSTMPH_0 (interrupt workaround)
>    4. Read TXSTMPL_0 (detect changes vs baseline)
> 
> Fixes: c789ad7cbebc ("igc: Work around HW bug causing missing timestamps")
> Suggested-by: Avi Shalev <avi.shalev@intel.com>
> Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
> Co-developed-by: Song Yoong Siang <yoong.siang.song@intel.com>
> Signed-off-by: Song Yoong Siang <yoong.siang.song@intel.com>
> Signed-off-by: Chwee-Lin Choong <chwee.lin.choong@intel.com>
> ---
> v1: https://patchwork.ozlabs.org/project/intel-wired-lan/patch/20250918183811.31270-1-chwee.lin.choong@intel.com/
> v2: https://patchwork.ozlabs.org/project/intel-wired-lan/patch/20251127134927.2133-1-chwee.lin.choong@intel.com/
> v3: https://patchwork.ozlabs.org/project/intel-wired-lan/patch/20251127151137.2883-1-chwee.lin.choong@intel.com/
> 
> changelog:
> v1 -> v2
> - Added detailed comments explaining the hardware bug workaround and race
>      detection mechanism
> v2 -> v3
> - Removed extra export file added by mistake	
> v3 -> v4
> - Added co-developer
> ---
>   drivers/net/ethernet/intel/igc/igc_ptp.c | 43 ++++++++++++++----------
>   1 file changed, 25 insertions(+), 18 deletions(-)
> 

Tested-by: Avigail Dahan <avigailx.dahan@intel.com>

      parent reply	other threads:[~2025-12-29 14:52 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-28 10:53 [PATCH iwl-net v4] igc: fix race condition in TX timestamp read for register 0 Chwee-Lin Choong
2025-12-02  2:11 ` Vinicius Costa Gomes
2025-12-29 14:52 ` Avigail Dahan [this message]

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