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From: Vignesh Raghavendra <vigneshr@ti.com>
To: Meghana Malladi <m-malladi@ti.com>, Nishanth Menon <nm@ti.com>
Cc: Tero Kristo <kristo@kernel.org>, Rob Herring <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<netdev@vger.kernel.org>, <srk@ti.com>, <danishanwar@ti.com>
Subject: Re: [PATCH v3 1/2] arm64: dts: ti: k3-am642-evm: Add ICSSG0 overlay for dual EMAC support
Date: Sat, 14 Mar 2026 18:01:01 +0530	[thread overview]
Message-ID: <8598edfa-4201-47b4-8929-be80dcca4617@ti.com> (raw)
In-Reply-To: <20260311053852.1034244-2-m-malladi@ti.com>

Hi

[...]

On 11/03/26 11:08, Meghana Malladi wrote
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-icssg0.dtso b/arch/arm64/boot/dts/ti/k3-am642-evm-icssg0.dtso
> new file mode 100644
> index 000000000000..f19acf1896c3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am642-evm-icssg0.dtso
> @@ -0,0 +1,168 @@
> +// SPDX-License-Identifier: GPL-2.0-only OR MIT
> +/**
> + * DT overlay for enabling ICSSG0 dual EMAC on AM642 EVM
> + *
> + * AM642 EVM Product link: https://www.ti.com/tool/TMDS64EVM
> + * DP83TG720 daughter card link: https://www.ti.com/tool/DP83TG720-IND-SPE-EVM
> + *
> + * Copyright (C) 2020-2026 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include "k3-pinctrl.h"
> +
> +&{/} {
> +	icssg0_eth: icssg0-eth {
> +		compatible = "ti,am642-icssg-prueth";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pru_icssg0_rgmii1_pins_default>, <&pru_icssg0_rgmii2_pins_default>;
> +		sram = <&oc_sram>;
> +
> +		dmas = <&main_pktdma 0xc100 0>, /* egress slice 0 */
> +		       <&main_pktdma 0xc101 0>, /* egress slice 0 */
> +		       <&main_pktdma 0xc102 0>, /* egress slice 0 */
> +		       <&main_pktdma 0xc103 0>, /* egress slice 0 */
> +		       <&main_pktdma 0xc104 0>, /* egress slice 1 */
> +		       <&main_pktdma 0xc105 0>, /* egress slice 1 */
> +		       <&main_pktdma 0xc106 0>, /* egress slice 1 */
> +		       <&main_pktdma 0xc107 0>, /* egress slice 1 */
> +		       <&main_pktdma 0x4100 0>, /* ingress slice 0 */
> +		       <&main_pktdma 0x4101 0>; /* ingress slice 1 */


Any particular reason to use ASEL = 0 unlike every other definition of
main_pktdma that uses ASEL=15?

> +		dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
> +			    "tx1-0", "tx1-1", "tx1-2", "tx1-3",
> +			    "rx0", "rx1";
> +
> +		interrupt-parent = <&icssg0_intc>;
> +		interrupts = <24 0 2>, <25 1 3>;
> +		interrupt-names = "tx_ts0", "tx_ts1";
> +
> +		ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>;
> +		firmware-name = "ti-pruss/am64x-sr2-pru0-prueth-fw.elf",
> +				"ti-pruss/am64x-sr2-rtu0-prueth-fw.elf",
> +				"ti-pruss/am64x-sr2-txpru0-prueth-fw.elf",
> +				"ti-pruss/am64x-sr2-pru1-prueth-fw.elf",
> +				"ti-pruss/am64x-sr2-rtu1-prueth-fw.elf",
> +				"ti-pruss/am64x-sr2-txpru1-prueth-fw.elf";
> +
> +		ti,pruss-gp-mux-sel = <2>,	/* MII mode */
> +				      <2>,
> +				      <2>,
> +				      <2>,	/* MII mode */
> +				      <2>,
> +				      <2>;
> +
> +		ti,mii-g-rt = <&icssg0_mii_g_rt>;
> +		ti,mii-rt = <&icssg0_mii_rt>;
> +		ti,iep = <&icssg0_iep0>,  <&icssg0_iep1>;
> +		ti,pa-stats = <&icssg0_pa_stats>;
> +

-- 
Regards
Vignesh
https://ti.com/opensource


  reply	other threads:[~2026-03-14 12:31 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-11  5:38 [PATCH v3 0/2] Add ICSSG0 dual EMAC support for AM642 EVM Meghana Malladi
2026-03-11  5:38 ` [PATCH v3 1/2] arm64: dts: ti: k3-am642-evm: Add ICSSG0 overlay for dual EMAC support Meghana Malladi
2026-03-14 12:31   ` Vignesh Raghavendra [this message]
2026-03-19 17:58     ` Malladi, Meghana
2026-03-11  5:38 ` [PATCH v3 2/2] arm64: defconfig: Enable DP83TG720 PHY driver Meghana Malladi

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