From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC26B5229 for ; Wed, 19 Jul 2023 07:11:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4D01EC433C7; Wed, 19 Jul 2023 07:11:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1689750710; bh=vQXnPTJwOFXKS8OGeyQepIwHUWfefqjc0NtH7P9v39k=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=iYB+sogwyp5LUVKrzUpQbFXw52Vv8gSPJxknBhhuIj2nVIptrf52/WQtAqlK2laff VLWB/JU9zGiqRQDd+HcXfBxgD6kd1T9fvf3HfW7a38YvlyZuYNtQQLS7kz90eQNVRx RJge8MroFQNJ27q/adaB3+ko75DCPMcseILvYpQ5F3cxohJejfLQqSnmkVpoBTDk2R NPtEUbEQ5pqTZgzBcW15iOW3hUl+UAVVkr5eFjr4On1qo1dAnk1eZ4DDESwt6ps/BW y7v9wm4qTiOWKp7TYiqw4q+AB93zdggVk3dp2620M5HaMOmYAP3PT64QhRQnMd0XPE Pf/r0Ko0mjuiw== Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Wed, 19 Jul 2023 09:11:44 +0200 From: Michael Walle To: Andrew Lunn Cc: Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Yisen Zhuang , Salil Mehta , Florian Fainelli , Broadcom internal kernel review list , =?UTF-8?Q?Marek_Beh=C3=BAn?= , Xu Liang , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Simon Horman Subject: Re: [PATCH net-next v3 02/11] net: phy: introduce phy_has_c45_registers() In-Reply-To: <7be8b305-f287-4e99-bddd-55646285c427@lunn.ch> References: <20230620-feature-c45-over-c22-v3-0-9eb37edf7be0@kernel.org> <20230620-feature-c45-over-c22-v3-2-9eb37edf7be0@kernel.org> <7be8b305-f287-4e99-bddd-55646285c427@lunn.ch> Message-ID: <867ae3cc05439599d63e4712bca79e27@kernel.org> X-Sender: mwalle@kernel.org Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit >> diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c >> index a64186dc53f8..686a57d56885 100644 >> --- a/drivers/net/phy/phy-core.c >> +++ b/drivers/net/phy/phy-core.c >> @@ -556,7 +556,7 @@ int __phy_read_mmd(struct phy_device *phydev, int >> devad, u32 regnum) >> >> if (phydev->drv && phydev->drv->read_mmd) { >> val = phydev->drv->read_mmd(phydev, devad, regnum); >> - } else if (phydev->is_c45) { >> + } else if (phy_has_c45_registers(phydev)) { > > This i would say should be > > phy_has_c45_transfers(phydev). This is about, can we do C45 transfers > on the bus, and if not, fall back to C45 over C22. Shouldn't this then be a bus property? I.e. mdiobus_has_c45_transfers(). I've have a similar helper introduced in 9/11: static inline bool mdiobus_supports_c45(struct mii_bus *bus) { return bus->read_c45 && !bus->prevent_c45_access; } >> static int phylink_sfp_connect_phy(void *upstream, struct phy_device >> *phy) >> diff --git a/include/linux/phy.h b/include/linux/phy.h >> index 11c1e91563d4..fdb3774e99fc 100644 >> --- a/include/linux/phy.h >> +++ b/include/linux/phy.h >> @@ -766,6 +766,11 @@ static inline struct phy_device >> *to_phy_device(const struct device *dev) >> return container_of(to_mdio_device(dev), struct phy_device, mdio); >> } >> >> +static inline bool phy_has_c45_registers(struct phy_device *phydev) >> +{ >> + return phydev->is_c45; >> +} > > And this is where it gets interesting. I think as a first step, you > should implement the four functions: > > phy_has_c22_registers() > phy_has_c45_registers() > phy_has_c22_transfers() > phy_has_c45_transfers() > > based on this. So there is initially no functional change. > > > You can then change the implementation of _transfers() based on what > the MDIO bus can do, plus the quirk for if a FUBAR microchip PHY has > been found. See above. Shouldn't it be mdiobus_...() then? > Then change the implementation of _registers() based on the results of > probing for the ID registers. So this is where I cannot follow. Right now there is (1) probing via bus scan (2) probing via DT (or maybe also ACPI) With (1) you we have scan_c22(), so if successful, phy_has_c22_registers() will return true, right? But it's not that clear for phy_has_c45_registers(), because sometimes we prevent that scan. So the PHY might have c45 but we don't know. For (2) we don't even do a c22 scan if we know if its a C45 PHY (or the other way around). I'm not sure we can reliably tell (at the end of this series) if a phy has c22 register, c45 registers or both. -michael > That should give us a basis for a clean separation between register > spaces and bus transaction, and then adding C45 over C22 should be > more obviously correct. > > Andrew