Re: [PATCH] net: mvpp2: add delay at the end of .mac_prepare

Baruch Siach
2022-05-01T07:57:17Z

Hi Marcin,

On Thu, Apr 28 2022, Baruch Siach wrote:
> On Thu, Apr 28 2022, Marcin Wojtas wrote:
>> I booted MacchiatoBin doubleshot with DT (phy-mode set to "10gbase-r")
>> without your patch and the 3310 PHY is connected to 1G e1000 card.
>> After `ifconfig eth0 up` it properly drops to SGMII without any issue
>> in my setup:
>>
>> # ifconfig eth0 up
>> [ 62.006580] mvpp2 f2000000.ethernet eth0: PHY
>> [f212a600.mdio-mii:00] driver [mv88x3310] (irq=POLL)
>> [ 62.016777] mvpp2 f2000000.ethernet eth0: configuring for phy/sgmii link mode
>> # [ 66.110289] mvpp2 f2000000.ethernet eth0: Link is Up - 1Gbps/Full
>> - flow control rx/tx
>> [ 66.118270] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
>> # ifconfig eth0 192.168.1.1
>> # ping 192.168.1.2
>> PING 192.168.1.2 (192.168.1.2): 56 data bytes
>> 64 bytes from 192.168.1.2: seq=0 ttl=64 time=0.511 ms
>> 64 bytes from 192.168.1.2: seq=1 ttl=64 time=0.212 ms
>
> This is what I see here:
>
> [ 46.097184] mvpp2 f2000000.ethernet eth0: PHY [f212a600.mdio-mii:02] driver [mv88x3310] (irq=POLL)
> [ 46.115071] mvpp2 f2000000.ethernet eth0: configuring for phy/10gbase-r link mode
> [ 50.249513] mvpp2 f2000000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
> [ 50.257539] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
>
> It is almost the same except from the link mode. Why does it try sgmii
> even before auto-negotiation takes place?

I have now tested on my Macchiatobin, and the issue does not
reproduce. PHY firmware version here:

[ 1.074605] mv88x3310 f212a600.mdio-mii:00: Firmware version 0.2.1.0

But still I see that pl->link_config.interface is initially set to
PHY_INTERFACE_MODE_10GBASER:

[ 13.518118] mvpp2 f2000000.ethernet eth0: configuring for phy/10gbase-r link mode

This is set in phylink_create() based on DT phy-mode. After interface
down/up sequence pl->link_config.interface matches the 1G wire rate:

[ 33.383971] mvpp2 f2000000.ethernet eth0: configuring for phy/sgmii link mode

Do you have any idea where your initial PHY_INTERFACE_MODE_SGMII comes
from?

Thanks,
baruch

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